Posts Tagged ‘simulation’
Wednesday, March 9th, 2016
In last week’s post on The Breker Trekker we summarized activities at the Design and Verification Conference and Exhibition (DVCon) in San Jose, including a brief mention of the “Redefining ESL” panel on Wednesday morning. I attended this session and took detailed notes in anticipation of blogging about it, but in the process gave some thought to my own opinions about the electronic system-level (ESL) domain and how they intersect with those of the panel participants.
The panel was organized by Dave Kelf of OneSpin Solutions and PR guru Nanette Collins, and moderated by Brian Bailey of SemiconductorEngineering. Brian is a long-time observer of the ESL market so I expected him to ask some tough questions. He opened by remarking that the term is generally credited to the late EDA analyst Gary Smith. Many of us who knew Gary sometimes teased him a bit on his regular pronouncements that “this will be the year of ESL.”
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Tags: Accellera, application, Breker, bring-up lab, Cadence, dvcon, emulation, ESL, FPGA, functional verification, graph, high-level synthesis, HLS, Imperas, mentor, node coverage, OneSpin, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, Synopsys, system-on-chip, test case generator, test cases, Universal Verification Methodology, use-case coverage, uvm, virtual platform, virtual prototype
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Thursday, March 3rd, 2016
We’ve just returned from our most important trade show of the year: the Design and Verification Conference and Exhibition (DVCon) in San Jose. Sure, DAC is a bigger show, but it covers all of EDA and so lacks the front-end digital focus of DVCon. We previewed the event over our last few blog posts and today we’d like to summarize what happened and make a prediction or two about how this particular DVCon will affect the industry.
The biggest news for us was that portable stimulus seemed to be on everyone’s lips this year. Many of the engineers who stopped by to visit our booth had heard the term and were aware that the Accellera Portable Stimulus Working Group (PSWG) is developing a standard. If they didn’t know what portable stimulus was, they almost surely knew by the end of the show.
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Tags: Accellera, application, Breker, bring-up lab, cache coherency, Cadence, Cavium, dvcon, emulation, ESL, FPGA, functional verification, graph, graph-based, mentor, multi-SoC, node coverage, path coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekApp, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm
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Wednesday, February 24th, 2016
We hope that the title of this blog post piqued your interest, because we don’t believe that we’ve seen anyone anywhere claiming to do automated multi-SoC verification at this level. Two weeks ago, we previewed next week’s Design and Verification Conference and Exhibition (DVCon) in San Jose. We highlighted one particular talk being co-presented by Breker and Cavium on “Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC” in the 9:00-10:30 a.m. session on Tuesday, March 1.
We teased you with the statement that this talk will describe “generating test cases for a multi-SoC configuration with well over 100 cores” and it’s time to tell you a bit more now that we have issued a press release on our project with Cavium. Of course, we need to reserve some of the details for the paper in the DVCon proceedings and the talk itself so that new material is being presented at the conference. We heartily encourage you at attend the show and hear for yourself.
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Tags: application, Breker, bring-up lab, cache coherency, Cavium, dvcon, emulation, FPGA, functional verification, graph, graph-based, multi-SoC, node coverage, path coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm
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Friday, February 19th, 2016
In last week’s post, we provided a preview of the program at the annual Design and Verification Conference and Exhibition (DVCon) in San Jose, coming up in ten days. We mentioned some of the interesting talks and other activities there, and focused in particular on “Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC” on Tuesday morning. The paper for this session was co-authored by Breker and Cavium, and both companies will present together at DVCon.
The paper and presentation describe the use of our Cache Coherency TrekApp and TrekSoC-Si to automatically generate self-checking, portable test cases for more than 100 CPU cores in a multi-SoC configuration in the Cavium bring-up lab. To set the stage for this story, today we’d like to revisit some of the reasons why cache coherency is so hard to verify and why an automated approach is the best solution.
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Tags: application, Breker, bring-up lab, cache coherency, Cavium, dvcon, emulation, FPGA, functional verification, graph, graph-based, MOESI, multi-SoC, node coverage, path coverage, portable stimulus, protocol, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm
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Wednesday, February 10th, 2016
Regular readers of The Breker Trekker know that we like to preview, review, and dissect technical conferences and trade shows that are of interest to verification engineers. Perhaps the conference we’ve covered the most has been the annual Design and Verification Conference and Exhibition (DVCon) in San Jose. As far as we know, this is the biggest event anywhere focused on digital and system design and verification, a nice complement to the analog-ish DesignCon.
As a matter of fact, DVCon has become so successful that there are now regional conferences in India and Europe in addition to the U.S. show. We’ve strongly supported DVCon India, including serving for all three years on the Promotions Committee, and have participated in DVCon Europe as well. But those are a bit in the future; DVCon (U.S.) 2016 is coming up in a just a few weeks. The program is online now, so we thought we’d review it and suggest some sessions of possible interest.
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Tags: application, Breker, bring-up lab, cache coherency, Cavium, dvcon, emulation, FPGA, functional verification, graph, graph-based, multi-SoC, node coverage, path coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm
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Wednesday, February 3rd, 2016
For more than four years now, Breker has branded itself as “The SoC Verification Company” and many people acknowledge our expertise in this domain. As we have discussed before on The Breker Trekker, our initial products focused on generating purely transactional tests for a simulation testbench, usually compliant with the Accellera Universal Verification Methodology (UVM) standard. When we extended our products to generate C code that runs on the embedded processors found within SoCs, we delivered on our “tagline” promise.
Since our early focus on simulating an SoC, we have expanded our technology and our product line to generate C test cases that run on embedded processors in emulation, FPGA prototypes, and actual silicon in the bring-up lab. In talking about what we do, we struggle to choose between “SoC” and “system” since for many of our customers the terms are synonymous. But we also have users verifying multi-SoC systems, and today we’d like to address that topic.
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Tags: application, Breker, bring-up lab, cache coherency, dvcon, emulation, FPGA, functional verification, graph, graph-based, multi-SoC, node coverage, path coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm
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Wednesday, January 6th, 2016
It’s been more than a year since we presented the Breker view of system coverage in detail, so it’s time to revisit the topic. We first defined the notion of system coverage as measuring which realistic, system-level application scenarios have been exercised using the existing test cases. We then demonstrated how our graph-based scenario models are ideally suited to capture system coverage metrics and fine-tune them using graph constraints if needed.
More recently, we noted that the term “use cases” has become more widespread and introduced the example of a digital camera SoC to show the types of use cases that should be exercised. The measurement for this exercise is also system coverage, so the bottom line is that all these terms are really talking about the same thing. Using a regular expression, we might say:
[application|realistic] (scenario|use-case) coverage = system coverage
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Tags: Accellera, application, Breker, functional verification, graph, graph-based, node coverage, path coverage, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, system coverage, test case generator, Universal Verification Methodology, use-case coverage, uvm
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Wednesday, December 30th, 2015
It’s becoming somewhat of a tradition here on The Breker Trekker blog to close each year with a list of gifts available from us to verification engineers. We started the series two years ago with an initial list focusing on our core benefits of automatic test case generation, system coverage, and reuse both vertically (IP to system) and horizontally (simulation to silicon). Last year’s post offered five more gifts reflecting additional products and new features added to our overall solution:
#5: Easier sequence specification in UVM testbenches.
#4: Faster coverage closure in UVM testbenches.
#3: Integration of system coverage with other coverage metrics.
#2: Debug of automatic test cases using standard tools.
#1: A fully automated solution for cache coherency verification.
Every one of the ten gifts from 2013 and 2014 is still available today for our customers. In addition, we have continued to evolve our Trek family of products and to deploy it on ever more challenging SoC verification projects. Without further ado, here is our all-new list of holiday gifts for the verification engineer in 2015:
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Tags: acceleration, Accellera, Breker, coherency, coverage, EDA, emulation, FPGA prototyping, functional verification, graph, level shifters, low power, platforms, portable stimulus, power domains, PSWG, reuse, scenario model, silicon, simulation, SoC, SoC verification, system coverage, test generation, TrekApp, TrekSoC, TrekSoC-Si, TrekUVM, use cases, uvm, verification IP, VIP, virtual
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Tuesday, December 22nd, 2015
In last week’s blog post, I reported from the recent 16th International Workshop on Microprocessor Test and Verification (MTV) in Austin. I focused mostly on the panel “Portable Stimulus and Testbenches – Possibilities or Wishful Thinking?” that included representatives from ARM, Cadence, Mentor, Synopsys, Freescale (now NXP), and Breker (yours truly). The panel was most enjoyable, but only one of several highlights for me at MTV.
This week, I’d like to touch briefly on some of the talks and topics on the technical program that caught my ear. These reflected a number of research frontiers for verification as well as several real-world case studies of SoC design projects tackling tough verification challenges. Perhaps the best moment for me was hearing Altera, one of our customers, describe how they used our products successfully on a recent design.
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Tags: Accellera, AMD, ARM, austin, Avago, Breker, Cadence, EDA, FPGA, Freescale, functional verification, graph, graph-based, mentor, MTV, node, NVIDIA, portable stimulus, PSWG, scenario model, simulation, SoC verification, Sudoku, Synopsys, test generator
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Wednesday, December 16th, 2015
Do you want to hear all the behind-the-scenes dirt from a workshop on the future of the MTV cable channel? Well, you’ll have to look elsewhere. “MTV” in this case means the International Workshop on Microprocessor Test and Verification, which celebrated its 16th incarnation in Austin two weeks ago. Although the name of the workshop has officially expanded to “Microprocessor and SOC Test and Verification” rest assured that the delightfully ambiguous abbreviation “MTV” will remain.
This was only my second time at this event, but I wish that I had been able to attend more. The setting is the top floor of the Hyatt Regency, with great views of Lady Bird Lake (formerly Town Lake) and downtown Austin. However, I noticed that recent high-rise construction has now blocked the sight of the Texas State Capitol from the hotel. The view might be distracting if not for the fact that the technical committee put together an interesting and diverse program, including a panel on portable stimulus.
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Tags: Accellera, ARM, austin, Breker, Cadence, EDA, emulation, FPGA, Freescale, functional verification, graph, graph-based, horizontal reuse, mentor, MTV, node, portable stimulus, PSWG, scenario model, silicon, simulation, SoC verification, Synopsys, test generator, vertical reuse
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