Posts Tagged ‘scheduling’
Thursday, December 10th, 2015
The past two weeks, we’ve been having a bit of fun playing alchemist and letting readers in on some of the deep, dark secrets of graph-based verification technology. This week, we conclude the series by showing some additional capabilities for our scenario models that are easy to control and view in a graph visualization. Our point is, of course, that graphs are a natural way to represent data flow and verification intent with no advanced degrees from MIT, IIT, or Hogwarts required.
As a quick reminder, graph-based scenario models begin with the end in mind and show all possible paths to create each possible outcome for the design. They look much like a reversed data-flow diagram, with outcomes on the left and inputs on the right. Breker’s Trek family can traverse the graph from left to right, randomizing selections to automatically generate test cases tailored to run in any target platform. Today, we continue using our example of a scenario model to verify that an automobile can move forward or stop.
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Tags: Accellera, Breker, constraints, cross-coverage, EDA, functional verification, goal, graph, graph-based, horizontal reuse, node, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, system-level coverage, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
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Thursday, December 3rd, 2015
Last week, we began exploring some of the ancient, mysterious powers of graph-based scenario models to show their power for verification and ability to capture the verification space, many aspects of the verification plan, and critical coverage metrics. We’re just kidding about the first part; there’s nothing at all mystical or magical about graphs. In fact, this series of posts is intended to show the opposite and demonstrate with a easy-to-follow example the value of graphs.
As we noted in our last post, graph-based scenario models are simple in concept: they begin with the end in mind and show all possible paths to create each possible outcome for the design. They look much like a reversed data-flow diagram, with outcomes on the left and inputs on the right. An automated tool such as Breker’s Trek family can traverse the graph from left to right, randomizing selections to generate test cases that can run in any target platform.
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Tags: Accellera, Breker, constraints, EDA, functional verification, goal, graph, graph-based, horizontal reuse, node, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
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Tuesday, November 24th, 2015
If there’s one thing that Breker is known for, it’s the use of graphs for verification. From our earliest days, we harnessed the abstraction and expressive power of graph-based scenario models to capture the verification space, many aspects of the verification plan, and critical coverage metrics. As we reported in a post a few weeks ago, it looks certain that the industry will follow our lead and base the upcoming standard from Accellera‘s Portable Stimulus Working Group (PSWG) on a graph representation.
As discussions have proceeded both within the PSWG and informally with interested parties, it has become clear that “graph” may not mean the same thing to all people. Our view of graphs is precisely defined in a way that makes it easy for users to create them and feasible for our tools to generated complex, multiprocessor test cases from them. Most of the key concepts can be communicated easily by the use of a familiar example, which we will begin in today’s post and continue next week.
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Tags: Accellera, Breker, EDA, functional verification, goal, graph, graph-based, horizontal reuse, node, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
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Friday, October 2nd, 2015
Anyone who has followed Breker for any length of time knows that our key technology is the ability to generate both Universal Verification Methodology (UVM) testbench transactions and C test cases running on SoC embedded processors automatically from graph-based scenario models. Yes, that’s a long sentence but it’s most of the “elevator pitch” that we might deliver to a potential investor or to a visitor at a trade show booth asking what we do.
For the purposes of today’s post, note that graphs are the root of the solution we provide. Ten years ago, when we first began talking about the idea of graphs as the basis for functional verification of complex chip designs, we were the proverbial pioneer with arrows in our back. But many successful customer engagements and the ever-rising need for better verification have validated our position. Graphs are clearly the “next big thing” in verification and we’d like to explain why.
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Tags: Accellera, Breker, Cadence, EDA, functional verification, graph, graph-based, horizontal reuse, mentor, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
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Wednesday, September 16th, 2015
Last week, we discussed the details of a noteworthy press release that we issued with Cadence and Mentor Graphics announcing a joint contribution to the Portable Stimulus Working Group (PSWG) of Accellera Systems Initiative. As we expected, this release stirred up a lot of interest in portable stimulus. The timing was perfect, both because of today’s deadline for contributions to the PSWG and because of last week’s DVCon India conference. I’d like to provide some updates on both activities.
First of all, the three companies did upload our joint contribution document to the PSWG internal Web site today in time for the deadline. Please note that, as per the rules for Accellera and most other standards groups, working documents are not available to the general public. If you’d like to see the contribution and follow the evolution of the standard, please consider joining the PSWG. If your company is not yet a member of Accellera, then please alert your standards manager to the benefits of participation.
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Tags: Accellera, Breker, Cadence, DVCon India, EDA, functional verification, graph, graph-based, horizontal reuse, mentor, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, SystemVerilog, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
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Tuesday, September 8th, 2015
This morning, Breker issued a press release with Cadence and Mentor Graphics announcing a joint contribution to the Portable Stimulus Working Group (PSWG) of Accellera Systems Initiative. We expect that this news may be surprising to much of the EDA world, so we’d like to take today’s post on The Breker Trekker to fill in some background and offer you the opportunity to ask questions. Please note that we are speaking only for Breker in this post although we doubtless share many opinions with our co-contributors.
Let’s start with a quick summary of how Accellera works so that all readers understand the context for this major contribution. The portable stimulus effort started with a Proposed Working Group last year that assessed the interest in a standard and defined a set of more than 100 requirements that such a standard would have to satisfy. Accellera approved the formation of the PSWG and we began meeting in March of this year. We have refined the requirements list and also developed a set of “use cases” showing the sort of real-world verification problems that a standard would have to address.
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Tags: Accellera, Breker, Cadence, EDA, functional verification, graph, graph-based, horizontal reuse, IEEE, mentor, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, subsystem, SystemVerilog, test, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
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Thursday, May 28th, 2015
Over the lifetime of this blog, we’ve covered a lot of diverse topics regarding Breker’s products and technology, trends in SoC verification, and the EDA industry in general. For the last month, we’ve offered our longest series of posts ever on a single topic: portable stimulus. There’s a very good reason for this: Accellera’s Portable Stimulus Working Group (PSWG) is making good progress on defining a standard in this area. As one of the group’s leaders, Breker has been leveraging our many years of experience in SoC verification to develop the best possible industry solution. We’ve been using The Breker Trekker blog to share our thoughts and to encourage your feedback.
We begin the fifth, and perhaps most important, post in our series by reminding you that we split portable stimulus into three layers: defining the tests using abstract primitive operations, scheduling the tests across multiple threads and multiple processors, and randomizing the control flow to verify the full range of realistic use-case scenarios. We have shown over the last two posts that both the first and second layers can be defined easily by a simple application programming interface (API) providing access to a base-class library. This library includes the basic building blocks needed for a directed or automated test as well as scheduling control for processors, threads, and resources. It is natural to wonder whether the randomization layer can be handled in a similar way.
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Tags: Accellera, API, Breker, C/C++, EDA, Esperanto, functional verification, graph, graph-based, horizontal reuse, IBM, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, subsystem, SystemVerilog, test, test generator, UML, Universal Verification Methodology, uvm, vertical reuse, VIP
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