Posts Tagged ‘mentor’
Thursday, July 30th, 2015
One of the signs that a technological domain is still fairly young is frequently evolving terminology as the pioneers attempt to explain to the mainstream what problem needs to be solved and what solutions can be brought to bear on the problem. Such is the case with SoC verification. At Breker we used to start explaining what we do by talking about graphs, but shifted to “graph-based scenario models” to emphasize that graphs are perfect for expressing scenarios of real-world behavior.
Our friends at Mentor, also strong advocates for graphs, began using the term “software-driven verification” to describe their approach. We rather like this description, but feel that it can only be applied accurately when embedded test code is being generated and when the embedded processors are in charge of the test case. Now our friends at Cadence have been sprinkling the term “use case” throughout their discussions on SoC and system verification. Let’s try to sort out what all this means.
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Tags: Accellera, Breker, Cadence, EDA, functional verification, graph, graph-based, mentor, PSWG, realistic use case, scenario model, simulation, SoC verification, test generator, Universal Verification Methodology, use case, uvm, VIP
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Thursday, April 16th, 2015
In last week’s post on The Breker Trekker blog, we surveyed the semiconductor market for the past 15 years or so from the standpoint of revenue leadership. Wikipedia provides a set of tables showing the top 20 semiconductor vendors for each year. We compiled this data into a single table, and found that this revealed some clear trends of how the industry has evolved during this period. The many spin-offs, mergers, acquisitions, and bankruptcies resulted in constant changes in the lower ranks of the top 20, and even some shuffling among the top players. This topic proved to be of great interest to our readers, with this week-old post surpassing many popular older posts.
Last week we also contrasted the semiconductor market with the EDA market, in which the top three revenue leaders have been the same for more than 20 years. Unlike semiconductors, there are almost no other EDA companies beyond the top three that were around 15-20 years ago and still exist today. We have had many spin-offs, mergers, acquisitions, and bankruptcies in our industry as well. Like semiconductors, we have had many changes in rankings beyond the very top tier, so we thought that we would try this week to create a similar chart and perform a similar analysis for EDA. However, this has not proven possible. We’d like to explain why and offer some more thoughts on the EDA market and how it differs from semiconductors.
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Tags: Agilent, Atrenta, Breker, Cadence, chip, EDA, functional verification, IHS, iSuppli, mentor, semiconductor, SoC, SoC verification, Synopsys, Virage
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Wednesday, April 8th, 2015
By some measures, the EDA market is a dynamic one. Many of our technological advances have come from startups and small companies, a list that gets refreshed as new market needs arise and as former independents get acquired or merge. The technology changes constantly to meet the needs of the semiconductor suppliers and system houses that are our customers. However, when it comes to market leadership EDA is incredibly static. The same three big companies have been at the top for more than 20 years now, we believe ever since Cadence swallowed Valid in 1991 and Synopsys moved into the third spot. Of course there has been some shuffling among Cadence, Synopsys, and Mentor, but that has happened only a few times.
This is in sharp contrast to the semiconductor business. Although Intel and Samsung have been at the top for more than ten years, several different companies have been number three and four during this period, with many shuffles along the way. There has been constant churn below the top slots, with several dramatic success stories for new vendors emerging during this same period. Since semiconductor companies are a main source of sales for EDA, we pay a lot of attention to the market and how it evolves. In this post we show one noteworthy market assessment and discuss some of the reasons for the changes and some of the implications for the industry as a whole.
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Tags: Breker, Broadcom, Cadence, chip, EDA, Freescale, functional verification, Hynix, IHS, Intel, iSuppli, Marvell, mentor, Micro, NVIDIA, Qualcomm, Renesas, Samsung, semiconductor, SoC, SoC verification, Synopsys, Toshiba, Valid
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Tuesday, December 16th, 2014
Much as we like informing you about the latest technical advances at Breker and weighing in on various industry topics, we love to take a break every so often and welcome a guest blogger. The EDACafé statistics show that these usually draw very well, and doubtless they attract a varied set of readers. This week we’re delighted to welcome back emulation expert and verification consultant Lauro Rizzatti, who has chosen to provide us with a fun look at the art and science of naming EDA companies and their products:
What’s in a name? Apparently, plenty. Let’s dispense some holiday cheer, kick back and forgo any technical discussion for a look at how a few companies in our industry got their names. Naming companies and products is big business. In fact, an entire industry is devoted to coming up with the perfect name to neatly express a company’s mission and the product portfolio. In some cases, though, companies stick closer to their employees and have contests where they can suggest names. That’s how OneSpin Solutions got its name. An R&D consultant in the U.K. came up with the name and won a case of beer for his efforts.
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Tags: Breker, Cadence, Carbon, EDA, emulation, functional verification, IPextreme, mentor, Palladium, Plunify, Protium, scoreboard, Synopsys, ZeBu
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Friday, October 3rd, 2014
Over the last several blogs posts, we’ve twice previewed the very first DVCon India show, celebrating it as a sign of India’s ever-growing importance in the electronics industry. We also mentioned that our co-founder and CEO Adnan Hamid would be presenting in two tutorials and helping to staff our booth in the exhibition. Now that the event is over and Adnan has returned from his travels, we’d like to fill you in what turned out to be a great event.
We have heard nothing but positive comments from attendees, vendors, and organizers. The conference was well attended, full of strong technical content, and well run. Perhaps the dominant theme to emerge was the importance of the “portable stimulus” effort undertaken by Accellera and the solutions available to meet some or all of the vision. It may be a stretch to call DVCon India the “Portable Stimulus Conference” but surely the first day (Thursday) was “Portable Stimulus Day” and we’ll explain why.
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Tags: Accellera, Bangalore, Breker, Cadence, CVC, DV, dvcon, ESL, functional verification, India, mentor, Synopsys, uvm
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Tuesday, September 9th, 2014
What verification engineer doesn’t love the occasional conference? It’s a chance to get out of the cubicle farm, hang out with colleagues from other companies, listen to stimulating technical talks, and catch up on what EDA, IP, and semiconductor vendors have been doing. Even in a time of tight travel budgets, the right conference can provide dividends far beyond its cost. There are a lot of smart people in the electronics industry and it’s valuable to share problems and solutions with them.
There are actually quite a few conferences and trade shows that have interesting verification content and draw significant numbers of verification engineers. One of the most-read posts in the history of The Breker Trekker blog was a discussion on which conferences verification engineers like best. We are constantly evaluating which events provide the most value to us and our customers, and find ourselves in the unusual position of having four shows scheduled in four locations over the next four weeks.
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Tags: Accellera, apps, ARM, austin, Bangalore, Boston, Breker, Cadence, coherency, CVC, DV, dvcon, ESL, functional verification, India, mentor, Newton, Santa Clara, SNUG, Synopsys, TechCon, TrekSoC, TrekSoC-Si, TrekUVM, uvm
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Friday, August 29th, 2014
As anyone involved in chip development knows, one of the biggest events of the year is the Design and Verification Conference and Exhibition, DVCon, which has been held for many years in San Jose. I’ve frequently shared my thoughts on this show and its importance to the industry in this blog. In just four weeks, DVCon expands to Bangalore for the very first DVCon India show. The full program for September 25-26 is now online and I’d like to focus on a few highlights from my perspective.
The first thing to note is the breadth of material being covered. The technical track is split between electronic system level (ESL) and design and verification (DV) topics, with a slight edge to the latter in terms of overall sessions. There are as many as five tracks in parallel, which is quite an accomplishment for a brand-new event. I know that there were many excellent session proposals submitted, which means that those selected are likely to be of high quality and wide interest.
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Tags: Accellera, Bangalore, Breker, Cadence, CVC, DV, dvcon, ESL, functional verification, India, mentor, Synopsys, uvm
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Monday, June 30th, 2014
I’ve written about formal analysis rather frequently in this blog, although I do not consider Breker’s products to be formal in nature. There are several reasons for this. After ten years working with formal tools, I remain personally interested in that market. I also see interesting parallels between the adoption of formal and graph-based technologies. Further, whenever we cover formal analysis we get a great response. Clearly our readers like the topic as well.
I’m returning to formal this week because of a provocative comment made by one of our customers at DAC a few weeks ago. Wolfgang Roesner from IBM participated on the show floor in a Pavilion Panel called “The Asymptote of Verification.” Among several astute observations about the attributes of graph-based scenario models, he made a comparison with formal analysis that I found especially perceptive.
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Tags: Accellera, assertions, Breker, coverage, EDA, formal, functional verification, graph, mentor, pwg, reuse, scenario model, SoC verification, standards, test generation, working group
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Tuesday, May 13th, 2014
As regular readers know, Breker’s claim to fame is the automatic generation of multi-threaded, self-verifying test cases that run on multiple heterogeneous processors within an SoC. The source for the generation process is a graph-based scenario model that captures the design intent and verification space. We chose graphs as an enabling technology more than ten years ago for a number of reasons, some of which we’ll discuss in this post.
The catalyst for this discussion is a new effort within the Accellera standards body to form the Portable Stimulus Specification Proposed Working Group (PWG). Basically, Accellera has formed a proposed working group to determine whether a technical working group should be established to start developing a specification for a standard. What does this have to do with graphs, and Breker? We’ll do our best to explain the history and current status.
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Tags: Accellera, Breker, Cadence, EDA, functional verification, graph, mentor, pwg, reuse, scenario model, SoC verification, standards, test generation, working group
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Tuesday, April 22nd, 2014
Yesterday may well go down in EDA history as one of the most important days in the evolution of the market for formal analysis. If you had asked me why yesterday morning, I would have said it was because I was attending the third “Decoding Formal Club” meeting sponsored by formal consulting experts Oski Technology. The range of companies represented there, and the enthusiasm for the topic, was a clear indication that formal has become an A-list technology for many verification teams.
So I planned to write today’s post about this meeting. But then, just as it was ending and Oski was thanking all the participants, news broke that Cadence had acquired formal leader Jasper Design Automation for $170M. Of course, this news was of intense interest to the attendees. It made yesterday “Acquisition Day” for formal analysis, so I’ll dub it “A-Day” and provide some thoughts in this post. I will talk a bit about the meeting as well, but will go into more details about the material presented in a future post.
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Tags: 0-In Design Automation, Breker, Cadence, EDA, equivalence checking, formal analysis, functional verification, jasper, mentor, simulation, SoC verification, Synopsys, Verplex
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