Archive for the ‘portable stimulus’ Category
Thursday, March 5th, 2015
In last week’s blog post on The Breker Treker we previewed this week’s Design and Verification Conference (DVCon) in San Jose, the leading industry event for verification professionals. We had a really good time there, finishing up just this afternoon. We always enjoy DVCon, but this week was even more fun than usual. We met attendees from an amazing range of companies designing SoCs, from simple microcontrollers to some of the largest FPGAs and custom chips on the planet.
Three aspects of the show really stood out: intense interest in cache coherency verification, considerable curiosity about the Accellera Portable Stimulus Working Group (PSWG), and the number of people who started the conversation with “I’ve heard good things about Breker from a colleague” or “I was told that I really need to check you out.” Let’s discuss what each of these trends means for the industry and speculate about the impact on Breker.
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Tags: Accellera, ARM, Breker, cache coherency, Carbon, CPAK, DesignCon, dvcon, DVCon Europe, DVCon India, EDA, functional verification, integration verification, IP, portable stimulus, SoC verification, standards, Trek, TrekApp, TrekSoC, verification IP, VIP
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Tuesday, February 24th, 2015
Most of the time when we blog about upcoming conferences, report live from an ongoing show, or summarize one that’s just finished, we see a significant spike in readership. Clearly our followers want to keep up with what’s happening in trade shows, conferences, and other industry events. It may also be the case that tighter travel budgets have reduced the ability to attend conferences in person, driving all the more interest in reading the news from the field. A few weeks ago, we discussed DesignCon and explained how it had evolved to include almost no verification content.
Next week is the annual Design and Verification Conference (DVCon) in San Jose, an event that we have covered in considerable detail in several popular posts in the past. As we have discussed, this conference has become the main way to keep up on what’s happening in the ever-changing world of functional verification. We encourage you to check out their Web site and the complete program. The topics include the UVM, SystemVerilog, SystemC, code generation, multi-language, mixed-signal, formal techniques, coverage metrics, and low-power verification.
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Tags: Accellera, Breker, cache coherency, Carbon, CPAK, DesignCon, dvcon, EDA, functional verification, integration verification, IP, portable stimulus, standards, Trek, TrekApp, TrekSoC, verification IP, VIP
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Wednesday, February 18th, 2015
In any industry dominated by a few large companies, it is important for the smaller players to ensure that their products work well with the broader solutions from the majors. Recognizing this need, and sometimes encouraged by legal action, the large companies develop partnership programs to enable and even foster integration with their solutions. All this is true for the EDA business, where the “Big 3” work closely with many smaller vendors for the sake of their mutual customers.
In Breker’s case, we generate SoC test cases that run on a variety of software and hardware platforms. We do not build any of those platforms ourselves but we need to verify that our test cases can run properly on them. Accordingly, we are members of several important partnership programs and we work closely with other vendors to find and fix any interoperability issues before our customers run into them. In this week’s post, we focus on how we work with Synopsys, the EDA market leader.
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Tags: Accellera, Breker, debug, design IP, EDA, functional verification, graph, graph-based, HW SW, portable stimulus, scenario model, simulation, SNUG, SoC verification, test generation, Universal Verification Methodology, uvm, VC Apps, VCS, Verdi, verification IP, VIP
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Wednesday, February 11th, 2015
As you may have seen this morning, the EDA standards organization Accellera officially announced the formation of the Portable Stimulus Working Group (PSWG). This group has the charter to “develop the electronic industry’s first standard for portable test and stimulus. When completed and adopted, this standard will enable a single specification that will be portable from IP to full system and across multiple target implementations.”
Regular readers will note that this wording sounds very familiar. At Breker, we’ve been talking about vertical reuse from IP to SoC and horizontal reuse across all verification platforms for years. At times we’ve felt like pioneers with arrows in our back. The formation of the PSWG is a validation that we’ve been heading in the right direction. We’re excited to see the industry embracing the challenges of SoC verification and starting to work on a new standard to address these challenges.
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Tags: acceleration, Accellera, Breker, bring-up lab, EDA, emulation, functional verification, graph, graph-based, portable stimulus, scenario model, simulation, SoC verification, test generation
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Thursday, February 5th, 2015
Two recent blog posts discussed what you should run when you first map your system-on-chip (SoC) design into an emulation platform and when you have your first fabricated chips from the foundry in your bring-up lab. We pointed out that trying to boot an operating system and run applications should not be the first step because production software is not designed to find and debug lingering hardware design errors. We recommended running the multi-threaded, multi-processor, self-verifying C test cases generated and optimized for hardware platforms by our TreSoC-Si product.
As you may know, TrekSoC uses the same graph-based scenario models as TrekSoC-Si, but optimizes the generated test cases for virtual prototypes, simulation, and simulation acceleration. In this post, we ask a similar question: what should you run in simulation when you first have the RTL for your SoC assembled and ready to be verified? Of course our answer will be the test cases generated by TrekSoC. However, there are some advantages of simulation over hardware platforms that foster a more extensive methodology for verification with Breker’s products.
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Tags: acceleration, Breker, bring-up lab, cache coherency, EDA, emulation, functional verification, graph, graph-based, portable stimulus, scenario model, simulation, SoC verification, test generation, TrekApp, TrekSoC-Si, use cases
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Tuesday, January 20th, 2015
Last week’s blog post raised the question of what you should run when you first map your system-on-chip (SoC) design into an emulation platform. We pointed out that trying to boot an operating system and applications immediately was a challenge because these are complex pieces of production software not designed to find lingering hardware design errors or to debug such errors easily even if detected. On many projects, the production software isn’t even available early enough to be used for design verification.
We strongly recommended running the multi-threaded, multi-processor, self-verifying C test cases generated by our Trek family of products. These “bare metal” test cases run on your SoC’s embedded processors at every stage of the project. TreSoC-Si specifically generates test cases tuned for emulation and FPGA prototype platforms. But what should you run when your fabricated chip first arrives back from the foundry? The answer is the same. TrekSoC-Si also generates test cases for silicon, ideal for use in your bring-up lab. Let’s explore this idea a bit more.
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Tags: acceleration, Breker, bring-up lab, EDA, emulation, functional verification, graph, portable stimulus, scenario model, simulation, SoC verification, test generation, TrekApp, TrekSoC-Si, use cases
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Wednesday, January 14th, 2015
Many of you are probably familiar with Lauro Rizzatti, who has written countless articles on the value of emulation for verifying system-on-chip (SoC) designs and been an occasional guest blogger here on The Breker Trekker. Lauro recently published an article in Electronic Engineering Times that really caught our attention. We could not possibly agree more with the title: “A Great Match: SoC Verification & Hardware Emulation” and, as we read through the article, were very pleased with the points he made.
Emulation involves mapping the RTL chip design into a platform that runs much like an actual chip, albeit considerably more slowly. The industry is not always consistent on its terminology, but generally if the platform is connected to a software simulation it’s being used as a simulation accelerator. In this case, the design’s inputs and outputs are connected to the simulation testbench much as they would be when running software simulation of the RTL. In emulation, there’s no simulator or testbench, and so the question becomes what to run on the design.
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Tags: acceleration, Breker, EDA, emulation, functional verification, graph, portable stimulus, scenario model, simulation, SoC verification, test generation, TrekApp, TrekSoC-Si, use cases
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Tuesday, December 23rd, 2014
As we predicted, last week’s guest post by Lauro Rizzatti on the origin of the names for some EDA companies and their products proved quite popular. We’ve found that mixing in some general industry news among the highly technical posts keeps our blog more lively and draws new readers, some of whom may tune in for the novelty but stay for the technology. Of course, we always welcome your comments as to whether or not we’re providing the type of content that’s interesting and valuable to you.
One naming story didn’t make it in before the deadline last week. Verific was one of the EDA companies asked about the origin of their name. President and COO Michiel Ligthart passed the question on to founder and CTO Rob Dekker, who said, “That will remain a mystery. But if you really want to know, ask the giraffe.” To find the giraffe, and maybe the answer, check out Verific’s Web site. To find the origin of the name “Breker Verification Systems” just continue reading. We promise to be less mysterious than Rob.
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Tags: Adnan Hamid, breaker, Breker, EDA, functional verification, portable stimulus, scoreboard, SoC verification, Verific
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Tuesday, December 16th, 2014
Much as we like informing you about the latest technical advances at Breker and weighing in on various industry topics, we love to take a break every so often and welcome a guest blogger. The EDACafé statistics show that these usually draw very well, and doubtless they attract a varied set of readers. This week we’re delighted to welcome back emulation expert and verification consultant Lauro Rizzatti, who has chosen to provide us with a fun look at the art and science of naming EDA companies and their products:
What’s in a name? Apparently, plenty. Let’s dispense some holiday cheer, kick back and forgo any technical discussion for a look at how a few companies in our industry got their names. Naming companies and products is big business. In fact, an entire industry is devoted to coming up with the perfect name to neatly express a company’s mission and the product portfolio. In some cases, though, companies stick closer to their employees and have contests where they can suggest names. That’s how OneSpin Solutions got its name. An R&D consultant in the U.K. came up with the name and won a case of beer for his efforts.
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Tags: Breker, Cadence, Carbon, EDA, emulation, functional verification, IPextreme, mentor, Palladium, Plunify, portable stimulus, Protium, scoreboard, Synopsys, ZeBu
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Tuesday, December 2nd, 2014
This blog focuses mostly on verification, but from time to time we like to take a look at other aspects of the EDA industry. Today we’d like to discuss high-level synthesis (HLS), its progress and status, and what’s keeping it from being a mainstream technology used for every chip design. It turns out that this topic has a lot to do with verification, so we’re not straying too far from our primary focus.
To start, let’s define what we mean by HLS in contrast to the mainstream technology of logic synthesis. Generating gates from a hardware description language (HDL) moved from a research problem to viable products around 1988. The ultimate winner among several promising companies was Synopsys, in part because they chose a register-transfer level (RTL) subset of the popular Verilog HDL as their input format. Their tools generated a gate-level netlist using the cells available in an ASIC vendor’s library.
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Tags: Breker, coverage, EDA, equivalence checking, ESL, formal analysis, functional verification, HDL, high-level synthesis, HLS, portable stimulus, reuse, RTL, scenario model, Verilog
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