Portable Stimulus – The First Verification Model

When people think about design languages, they may not realize that the language is almost irrelevant. The language supports the underlying semantic model and it is this model that is important. EDA has defined design models at the gate level, the register transfer level (RTL) and various forms of behavioral levels. When we talk about RTL, we think about Verilog and VHDL, but they are only the languages that support that model, or very minor variations of it. But what about verification?

Verification has never had a model. Verification has piggy-backed on the design languages. Attempts were made to develop verification languages in the 1980s, but none of them were successful and most of them were more directed towards test rather than functional verification. Additionally, it was designers who performed the bulk of verification at that time and they saw no need to learn multiple languages. Verilog and VHDL were designed with the primary application being the simulation of RTL semantics. The general attitude was that they were also good enough to describe the stimulus necessary for the verification task.

The development of languages such as e, Vera and then later SystemVerilog, changed the situation a little in that it acknowledged that verification had different requirements than design and that attempting to use the same language may not have been the best decision. Also at that time, verification groups had taken over much of the verification task from designers, and, given the rapid increase of verification complexity, were eager for better solutions. But still no model existed.

Most of the language advances concentrated on the act of supplying stimulus to the design under test rather than considering the act of verification itself. This supported the long standing simulation paradigm but failed to properly integrate the other aspects of verification, such as results checking and coverage.

The addition of the property specification languages, such as PSL and SVA (both of which have formally defined models that underlie the language) was the exception to this trend in that they defined sequences that inherently contained the expected behavior. While properties could be used in simulation as assertions, the primary target for them was formal analysis tools. That change of focus is probably the most important change that has happened to verification since the simulator was invented.

Portable Stimulus (PS) has learned from these earlier developments and extends the concepts of a design model into the verification space. It will become the first true verification model in several ways:

• It is independent from the execution engine that will be used to determine the behavior of the design
• It is agnostic of the tools that will operate on it
• It is a self-contained model that includes stimulus, response and coverage
• It is amenable to having constraints placed on it rather than in a separate file
• It makes verification composable in the same manner as design
• It acknowledges that a system is composed of hardware and software
• It is not derived from a design language
• It is language agnostic

Portable Stimulus is one level removed from an act of verification. It does not describe stimulus, it describes intended functionality and from that stimulus can be created. For example, from a portable stimulus model, a tool might be run which generates stimulus for simulation or a tool might generate formal properties. Tools can also be aware of the constraints associated with running a testcase on an emulator, or even first silicon when it comes back from the lap, and generate suitable testcases for those. There is no limit to the capabilities of tools that could run from this one verification model.

PS is more abstract than previous simulation languages. It hides many of the details about how behaviors may be implemented and instead concentrates only on the higher-level mechanisms that can affect behavior. For some people, this may raise warning flags, but that is the whole point of raising the abstraction. Verification, using portable stimulus, will only verify those behaviors that it has been exposed to and block-level verification, which concentrates on the detailed implementation, still needs to be done.

For example, an IP block may have many modes and behaviors and when verified in a standalone manner, all of those have to be fully verified. When that block is integrated in a system, a subset of modes and behaviors are actually used. It is only these used behaviors that would be verification targets at the higher level. All other behaviors would be unreachable by a graph traversal, which is how a tool would select a scenario to be generated and executed on a design under test.

PS would also be targeting behaviors that are deeply embedded in the state space of the design. The generation of such tests may take too long or be difficult to write and maintain by hand or with the existing verification methodologies.

The notion of a new model may seem scary to many, but there is more good news, thanks to the persistence of the user community within the standards effort. PS needs a language that supports the model semantics. There have been an army of language experts who understand how to construct good languages and the EDA industry can leverage those decades of experience without the need to reinvent a new language. The language supporting the model brings together two notions that are well known in the verification community already. The first of these is C++ which is at the heart of the language supporting the PS model and is a language that many of the stake holders in system-level design and implementation are intimately familiar with already.

The second notion used is graphs which are very frequently used by all groups within a design team to show control or data flows. The merging of these two concepts is very intuitive and thus there is very little new to be learned. Adoption is fast and the results are more than an order of magnitude better than the existing methods.

Breker has been evolving the notions of verification intent and portable stimulus models by forming long term partnerships with verification teams for over a decade. That expertise is now being shared with Accellera to create the eagerly awaited Portable Stimulus standard. Together we can do this.

Tags: Accellera, Breker, graphs, Language Agnostic, portable stimulus, SystemVerilog, Vera, Verification Model, Verilog, VHDL

Category: Knowledge Depot

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