Archive for August, 2016
Wednesday, August 24th, 2016
Three weeks ago, we published a post on The Breker Trekker blog that previewed some of the talks and tutorials on the technical program at the upcoming third Design and Verification Conference and Exhibition (DVCon) India on September 15-16 in Bangalore. More of the details on the conference are now available online, and for today we’d like to highlight some of the keynote addresses, panels, and poster sessions on the agenda that also stand out for us.
As always, the program and steering committees have put a lot of thought into keynote speakers who will take a wide view of not just the EDA industry, but the larger electronics industry that we serve. Mentor CEO Wally Rhines is always a great speaker who comes armed with lots of charts and statistics to support his positions. His talk on “Design Verification: Challenging Yesterday, Today and Tomorrow” will survey the history and evolution of verification while predicting some of the future challenges
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Tags: acceleration, Accellera, Breker, Broadcom, Cadence, coverage, debug, dvcon, DVCon India, EDA, emulation, FPGA prototyping, functional verification, graph, graph-based, Infineon, Intel, mentor, multi-SoC, multi-threaded, multiprocessor, NXP, portable stimulus, PSWG, Qualcomm, reuse, scenario model, simulation, SoC verification, software-driven verification, Synopsys, test generator, transactional, TVS, Universal Verification Methodology, UVC, uvm, VIP
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Thursday, August 18th, 2016
When we first began offering our Trek family of products for what’s now known as portable stimulus, we talked a lot about vertical and horizontal reuse. Vertical reuse means that you can create a scenario model for individual IP blocks and generate test cases to run in their UVM testbenches, then move up to clusters and subsystems. The IP models can simply be plugged together to form a higher-level model from which appropriate higher-level test cases can be generated.
At the full-SoC level, you can generate C test cases that run on your embedded processors. Horizontal reuse is the ability to move from simulation to hardware (acceleration/emulation, FPGA prototypes, and silicon) while generating appropriate tests for these platforms from the same SoC scenario model. We generally described both forms of reuse in a unidirectional flow. However, bidirectionality is very valuable and, we believe, essential for portable stimulus. Let’s cover that topic in today’s blog post.
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Tags: acceleration, applications, apps, bidirectional, Breker, cache coherency, coverage, debug, EDA, emulation, FPGA prototyping, functional verification, graph, horizontal reuse, multi-SoC, multi-threaded, multiprocessor, portable stimulus, scenario model, simulation, SoC verification, system coverage, transactional, TrekApp, TrekBox, TrekSoC, TrekSoC-Si, uvm, vertical reuse
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Wednesday, August 10th, 2016
As some of you may have seen, two years ago the IEEE created an app that ranks the popularity of dozens of programming languages. They use twelve different metrics, from search results and social media mentions to technical publications and requirements listed in job openings. If you don’t like the way that they use these metrics, you can create your own ranking using your own mix. It’s really quite a clever idea and it generates lots of discussion every year.
For 2014 and 2015, C held the #2 spot, just below Java in the rankings. The big news this year is that C has edged into first place, although the top two spots remain very close as measured by the metrics the IEEE has chosen to use. C++ was in the #3 spot for the past two years, but for 2016 flipped places with Python. As you all know, we are strong advocates of C/C++ for verification and so we’d like to share some thoughts on these results and what they mean for our industry.
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Tags: acceleration, Accellera, API, Breker, C/C++, EDA, emulation, FPGA prototyping, functional verification, graph, graph-based, horizontal reuse, IEEE, Java, Mentor Graphics, multi-SoC, multiprocessor, Perl, portable stimulus, programming languages, PSWG, Python, reuse, scenario model, simulation, SoC verification, software-driven verification, subsystem, SystemVerilog, test generator, testbench, Universal Verification Methodology, uvm, vertical reuse, VHDL
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Wednesday, August 3rd, 2016
As many of you know, in 2014 the longstanding Design and Verification Conference and Exhibition (DVCon) expanded beyond Silicon Valley to India. The first year of DVCon India was very successful for a new event, drawing more than 450 attendees from more than 80 companies and universities. Last year’s show grew to more than 600 engineers attending the technical program, visiting the vendor exhibition, and enjoying the numerous opportunities to network with their peers.
The third annual DVCon India will be held on September 15 and 16, once again at the Leela Palace in Bangalore. From our perspective, the show just keeps getting better and better every year. The full program is now available online, and for today’s post we’d like to mention some of the technical sessions that we think look especially interesting. In a future post, we’ll discuss other aspects of the program, including the keynote addresses.
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Tags: acceleration, Accellera, Breker, coverage, debug, dvcon, DVCon India, EDA, emulation, FPGA prototyping, functional verification, graph, graph-based, Infineon, IP-XACT, multi-SoC, multi-threaded, multiprocessor, NXP, performance analysis, portable stimulus, PSWG, reuse, scenario model, simulation, SoC verification, software-driven verification, test generator, transactional, Universal Verification Methodology, UPF3.0, UVC, uvm, VIP
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