Archive for September, 2014
Tuesday, September 23rd, 2014
This morning, our good friends at Carbon Design Systems announced a new Web portal to provide system-level solutions for system-on-chip (SoC) developers. The Carbon System Exchange provides a wide range of Carbon Performance Analysis Kits (CPAKs), pre-built systems or subsystems with software at the bare metal or operating system level. CPAKs are key building blocks for SoC teams creating complete virtual prototypes for their designs.
Breker is one of nine announced IP and EDA partners who are working with Carbon to create new CPAKs or enhance current offerings. Some partners, such as ARM, Arteris, and Cadence, are providing processor models or other forms of IP commonly found in SoCs. Others, such as Kozio and Breker, are providing software to run on the CPAKs. As you might expect, what we’re actually providing is not a fixed set of software, but rather the ability for CPAK users to generate multi-processor, multi-threaded, self-verifying C test cases.
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Tags: ARM, Breker, Carbon, coherency, coverage, CPAK, EDA, functional verification, graph, performance, scenario model, SoC verification, TrekSoC, TrekSoC-Si, use cases
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Wednesday, September 17th, 2014
One of the many challenges faced by small software companies is evolving their product lines in ways that make sense. New products must mesh with existing products so that customers can quickly understand what they might want. Products must be differentiated enough to stand separately, yet should leverage some of the same technology and expertise. Small companies have limited resources and it’s usually a mistake to develop multiple unrelated products requiring separate engineering teams.
Breker is no exception; we have a bunch of smart people with lots of ideas about how graphs can be applied to a wide range of problems. However, by focusing on the functional verification of large, complex chips using graph-based scenario models we are able to target a fairly specific group of companies and users. We also get tremendous productivity from a small R&D team because their collective knowledge spans the limited but important product range that we cover. This blog post is an attempt to describe that range more precisely.
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Tags: applications, apps, Breker, coverage, EDA, ESL, functional verification, graph, portable stimulus, products, reuse, scenario model, SoC verification, software-driven verification, transactional, Trek, TrekSoC, TrekSoC-Si, TrekUVM, UVC, uvm
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Tuesday, September 9th, 2014
What verification engineer doesn’t love the occasional conference? It’s a chance to get out of the cubicle farm, hang out with colleagues from other companies, listen to stimulating technical talks, and catch up on what EDA, IP, and semiconductor vendors have been doing. Even in a time of tight travel budgets, the right conference can provide dividends far beyond its cost. There are a lot of smart people in the electronics industry and it’s valuable to share problems and solutions with them.
There are actually quite a few conferences and trade shows that have interesting verification content and draw significant numbers of verification engineers. One of the most-read posts in the history of The Breker Trekker blog was a discussion on which conferences verification engineers like best. We are constantly evaluating which events provide the most value to us and our customers, and find ourselves in the unusual position of having four shows scheduled in four locations over the next four weeks.
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Tags: Accellera, apps, ARM, austin, Bangalore, Boston, Breker, Cadence, coherency, CVC, DV, dvcon, ESL, functional verification, India, mentor, Newton, portable stimulus, Santa Clara, SNUG, Synopsys, TechCon, TrekSoC, TrekSoC-Si, TrekUVM, uvm
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Tuesday, September 2nd, 2014
Three weeks ago, we introduced our TrekUVM product, a solution for automatically generating test cases to improve coverage of chips in transactional testbenches. We don’t sit still for long at Breker; today we’re introducing the first of a series of TrekApp (application) products that will address specific problems in the verification of SoCs and other large designs. The term “app” is well-known from smartphones and tablets, but also used more and more in EDA.
Apps are attractive for several reasons. They provide turnkey access to new technologies without the user having to become an expert. They solve problems that are well established as project bottlenecks, so a return-on-investment (ROI) analysis tend to be easy. They provide immediate value to the project team, reducing the cost of deployment and increasing the ROI. For SoC verification, we’ve chosen cache coherency as the first app to make available.
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Tags: applications, apps, Breker, coverage, EDA, functional verification, graph, portable stimulus, reuse, scenario model, SoC verification, transactional, TrekSoC, TrekSoC-Si, TrekUVM, UVC, uvm
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