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 The Breker Trekker
Tom Anderson, VP of Marketing
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »

Cache Coherency? Breker Provides An App for That

September 2nd, 2014 by Tom Anderson, VP of Marketing

Three weeks ago, we introduced our TrekUVM product, a solution for automatically generating test cases to improve coverage of chips in transactional testbenches. We don’t sit still for long at Breker; today we’re introducing the first of a series of TrekApp (application) products that will address specific problems in the verification of SoCs and other large designs. The term “app” is well-known from smartphones and tablets, but also used more and more in EDA.

Apps are attractive for several reasons. They provide turnkey access to new technologies without the user having to become an expert. They solve problems that are well established as project bottlenecks, so a return-on-investment (ROI) analysis tend to be easy. They provide immediate value to the project team, reducing the cost of deployment and increasing the ROI. For SoC verification, we’ve chosen cache coherency as the first app to make available.

Coherency has been a challenge for verification ever since the first CPU designs added caches to speed up memory access. Ensuring that the cache and main memory remained properly synchronized became an important verification step. Reading stale data could lead to all sorts of odd system problems that would be hard to debug. In today’s world of multi-core CPUs, multi-level caches, and complex memory subsystems, coherency is a harder problem than ever.

It turns out that graph-based scenario models are very good at generating the type of traffic that stresses SoC coherency. As we’ve discussed before, the test cases we generate with TrekSoC are multi-threaded so that many user-level scenarios can be run in parallel. We are also aggressive in the way that we allocate memory, abutting memory regions and reusing memory as soon as it’s freed so that any addressing error will cause a test case failure.

The result is that we have lots of threads running at once, with multiple CPUs accessing multiple memories and memory regions. The competition for bandwidth saturates the buses, interconnects, and memory channels. This stresses the cache coherency logic to find bugs otherwise impossible to catch before tape-out. It also generates a level of traffic sufficient to gather realistic performance metrics, identify system bottlenecks, and fine-tune the design as needed.

The Coherency TrekApp provides a graph-based scenario model pre-populated with most information needed to verify cache coherency. Of course, you need to provide the details of your system, including number of CPUs, number of threads, memory organization, and cache structure. We provide documentation, training, and applications support to walk you through the essential steps. If you would like an even more turnkey solution, we can offer consulting services as well.

This app has clear value for anyone designing a CPU subsystem. You might wonder about its applicability to SoC developers who are incorporating a complete CPU cluster from their processor vendor. At a minimum, our coherency app can be helpful to validate that the supplier has no lingering cache-related bugs. However, we often find that SoC designers are extending the coherency requirements beyond the pre-packaged processor IP.

They may be modifying certain aspects of the CPU subsystem that affects coherency. They may be connecting the subsystem to a custom memory controller or adding elements such as a DSP or GPU that must remain coherent with the CPUs. The resulting complicated coherency rules are a major verification challenge. In the x86 server case study available from our Web site, the design contained several elements that were asymmetrically or partially coherent.

We have already deployed this app on some production designs and have seen a big increase in system-level coverage achieved by TrekSoC’s automatic test cases versus traditional hand-written tests. The app has already shown that access to the benefits of graph-based scenario models can be provided in a turnkey fashion with minimal user effort. We’re excited about its promise for all SoC customers.

The Coherency TrekApp is the first in a series that we will provide. We’re working on a TrekApp for verification of low-power design structures and plan to offer apps to help program IP blocks for standard protocols. We expect that scenario model apps will help to grow our market much as formal apps did for formal analysis over the past ten years. We’d love to hear your thoughts on aspects of chip verification where an app might help.

Tom A.

The truth is out there … sometimes it’s in a blog.

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