Future of IP: from Tensilica to IPextreme

Bill Martin, President/VP of Engineering at E-System Design, has sent another thoughtful response to a blog regarding IP, in particular my post last week about the astonishing increase in the valuation of ARMH over the last 5 years.

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Years ago, Chris Rowen had a clear vision where EDA and IP would start to merge, given the complexities of both. He knew both could have a large impact on the resources and risks associated with creating an SoC. His vision was so compelling, Chris resigned from a great group within Synopsys to form his start-up, Tensilica.

At the time, EDA/IP/Customization were all difficult problems to resolve. By building larger blocks that automatically reconfigured and combined other aspects (examples: SW compiler/debugger for code that could add/delete instructions and a verification suite that reconfigured themselves based customers’ usage), the solution Chris created at Tensilica addressed SIP/Embedded SW/VIP and EDA.

Quite an ambitious undertaking, but over time as his solution was honed and matured, the industry saw the end result – a few months ago the large acquisition of Tensilica by Cadence. In fact, the deal was part of a trend. Look at the various EDA and IP acquisitions since 2008, those exceeding $100 million:

2008 – Synopsys acquired Synplicity: $227 million
2010 – Cadence acquired Denali: $315 million
2010 – Synopsys acquired VirageLogic: $315 million (includes ARC and their processors)
2011 – Ansoft acquired Apache: $314 million
2011 – Synopsys acquired Magma: $507 million
2013 – Cadence acquired Tensilica: $380 million (processor and subsystems based on it)

There were many other smaller acquisitions, as well. Cadence and Synopsys have purchased many smaller IP players to fill out their ‘line’ cards in recent years, well over a combined $1B on acquisitions.

It is clear that IP will continue to morph. I believe the next battle will be when large product developers (such as nVidia, Micron, etc.) determine if/when they will not only produce end products for purchase, but also start selling their older generation IP to be sold as embedded silicon/software components. Many issues need to be resolved both internally and externally for this to happen, and there might be restrictions on how or what markets these ‘super’ blocks can be used.

The good news, IPextreme’s business model is doing just that today with smaller complex blocks. IPextreme’s ‘line’ cards are similar products. The original developers (Freescale, NXP, NationalSemi, TI) have decided to expand their architectural reaches into custom products and have all signed up to allow access to some of their IP.

As we start to grow the solutions, the level of expertise required to create and validate these functions will most likely prevent IP consumers from ‘tweaking’ the component. You purchase and use it ‘as is’. The advancements in 2.5/3D packaging might enable this process even faster. Non-homogeneous solutions can take different silicon die and assemble an interposer with different die. A company such as IPextreme could be the distributor of these systems, removing licensing and support issues from the original developer.

Designing and ‘erecting’ silicon chips is not much different than building a skyscraper or home. The builders do not create all the components that are required. They purchase lots of components (I-beams, rivets, tempered glass, wiring, etc.) from various manufacturers and then they integrate them into the design. Why? Schedules, costs, expertise would be too great for the builders otherwise, building a skyscraper or house. A steel producer is able to produce higher quality steel at a lower cost than a builder can. Lowering the cost structures this way enables much more building, and at a faster pace. You can see the same phenomenon in auto or aero companies.

Over the next few years, it will be interesting to see how the ‘system’ companies start to enter the IP market at the silicon level. These changes are set to dramatically alter the IP and EDA markets.

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Bill Martin’s last commentary: Clarifying Accellera’s IP Tagging 1.0 Standard

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Tags: Ansoft, Apache, ARM, Bill Martin, Cadence, Chris Rowen, Denali, E-System Design, IPextreme, Magma, Synopsys, Synplicity, Tensilica, VirageLogic

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