2018 marked the first year of the Design Infrastructure Alley (DIA) at DAC.  It was the first time that DAC devoted floor-space to discussing the unique IT needs of the semiconductor industry.

Some of the big issues we are looking to address at DAC include:

Increased Focus on Data/IP Security

Semiconductor companies have traditionally had a very open, collegial way of working.  The emphasis was on making it easy for engineers to collaborate.  This was generally fine when companies created and owned virtually all of their own IP.  However, with the rise of third party IP (and the unique legal agreement for each set of IPs), it’s no longer acceptable to have “open access” to data.  This is a significant IT, engineering and business challenge that will require a great deal of work to correct without wreaking havoc with design schedules.

CAD flows which engineers have used for years will likely face challenges in a “locked down” environment, as the new rules will surely break an underlying data access assumption embedded deep within them.
Read the rest of Design Infrastructure Alley at DAC 2019

 The spots are limited and boards are provided as first come first served

Interested in showing off your talent in developing deep learning algorithms on embedded hardware platforms for solving real-world problems? Join us in the second System Design Contest (SDC) at the 56^th Design Automation Conference in 2019!

In 2018, DAC held its inaugural system design contest. The 2018 SDC featured a low-power object detection challenge (LPODC) on designing and implementing novel algorithms based object detection in images taken from unmanned aerial vehicles (UAV). Contestants compete in two different embedded hardware categories: FPGA (Xilinx PYNQ Z-1 board) and GPU (Nvidia Jetson TX2), provided by our premier platform sponsors, Xilinx and Nvidia, respectively. Datasets consisting of video clips captured in a UAV view and with different points of view are provided by our industry sponsor DJI.

Contestants use the provided training dataset to train their networks, and a hidden dataset is used to evaluate the performance of the designs in terms of accuracy, throughput and energy. Over 110 teams from both academia and industry of 11 different countries participated in the contest. Three winning teams were selected from each hardware category and received cash prizes sponsored by Nvidia and Xilinx. Winning teams listed below.

An even more exciting and competitive SDC will take place at the 56^th DAC to be held in Las Vegas, NV on June 2-6, 2019. The same datasets and hardware platforms as the SDC’18 contest will be used.  We expect that higher quality solutions will be submitted by participating teams. The organizers of SDC’19 are:

• Jingtong Hu (University of Pittsburgh),
• Jeff Goeders (Brigham Young University),
• Philip Brisk (University of California, Riverside),
• Yanzhi Wang (Northeastern University),
• Guojie Luo (Peking University),
• Chris Rowen (Cognite Ventures),
• Bei Yu (Chinese University of Hong Kong)
• Naveen Purushotham (Xilinx)

The schedule for SDC’19 contest are as follows:

November 30: Registration deadline

December 10: Host webinars to share resources available

February – May: Teams submit their solutions and update ranking list

June: Invited talks and demos at DAC, June 2-6, 2019

Visit the System Design Contest 2019 web page for more details and registration information.

The spots are limited and boards are provided as first come first served. So, make sure to register early!

2018 System Design Contest organizers and winning teams:

The 2018 SDC at the 55^th DAC was organized and managed by:

• Yiyu Shi (University of Notre Dame),
• Jingtong Hu (University of Pittsburgh),
• Chris Rowen (Cognite Ventures),
• Bei Yu (Chinese University of Hong Kong),
• Cong Zhao (DJI),
• Naveen Purushotham (Xilinx),
• Amit Goel (Nvidia)

2018 Winning Teams:

FPGA CATEGORY

First Place – TGIIF – Shulin Zeng, Weicong Chen, Tianhao Huang, Yujun Lin, Weizhe Meng, Zhenhua Zhu, Yu Wang – Tsinghua University

Second Place – SystemsETHZ –Kaan Kara, Ce Zhang, Gustavo Alonso –

ETH Zurich

Third Place – iSmart2– Cong Hao, Yuhong Li, Sitao Huang, Xiaofan Zhang, Tianqi Gao, Jinjun Xiong, Kyle Rupnow, Haufeng Yu, Wen-Mei Hwu, Deming Chen – University of Illinois at Urbana-Champaign

GPU CATEGORY

First Place – ICT-Jeejio – Hao Lu, Xuyi Cai, Xiandong Zhao, Ying Wang – Institute of Computing Technology, Chinese Academy of Science

Second Place – DeepZ – Jianing Deng, Cheng Zhuo – Zhejiang University

Third Place – SDU-Legend – Chuanqi Zang, Jie Liu, Yueming Hao, Shiqing Li, Miao Yu, Yango Zhao, Mingyi Li, Pengfei Xue, Xiaoyu Qin, Lei Ju, Xin Li, Mengying Zhao, Hongjun Dai – Shandong University

Some of the most valuable events at DAC are the IP Track sessions, which give small- and medium-sized companies a chance to share innovations that might not get much attention elsewhere.

The use of IP in SoCs has exploded in recent years. In a panel at DAC 2017, an industry expert noted that the IP market was clearly growing even faster than EDA itself, due to the fact that more and more chip makers are externalizing IP development functions.  This is similar to what happened with EDA tools in the 1990s.  The externalization trend is ongoing, and there is still more IP to be go. With continued advances in semiconductor processing, new systems-on-chip (SoCs) are always increasing in complexity.  Research firms estimate that some SoCs include up to 200 blocks of IP, licensed from multiple companies, ranging from an I/O cell all the way up to an Arm CPU. Identifying and acquiring or designing all of the IP blocks is just the beginning.  The big challenge is when you have to bring all of that IP into one design database and manage the versioning and design flow requirements of each unique block.

So, if you’re working to optimize your designs with IP, come check out the DAC IP track this year.  Most of our sessions consist of invited presentations and panels. We have nine 90-minute sessions total, from Monday through Wednesday of DAC week. Five of the sessions are for invited presentations—three 30-minute presentations each—and two for panels. The final two sessions will showcase submitted and reviewed presentations from industry and academia.  This year, the submissions seem to reflect the increased interest in IP-based design, as we received 25 percent more than we did last year.

One area that is hot across DAC this year is machine learning, perhaps no surprise given how much artificial intelligence and machine learning technology is proliferating in systems and in the media.  We have an IP for Machine Learning session that will be fascinating. Cambricon, an up-and-coming Chinese company, has created the first AI deep learning IP in the world. On Monday morning, they will present the details of their deep learning processor. In the same session, you’ll hear from Cadence, which has developed a neural processor based on its Tensilica architecture, and Dr. Vivienne Sze from MIT, who will discuss the types of hardware that are required for deep learning.

The IP track also includes two panels—one of which focuses on the perennially “hot” topic of low power. Industry editor John Blyler will moderate a panel that includes representatives from companies including TSMC, Microsoft and Minima, for  a wide-ranging discussion of the latest problems in achieving low power for new applications such as virtual reality wearables, IoT devices and even automotive systems.

The IP Track sessions are also a good opportunity for engineers to learn about some types of IP that most have not gotten a lot of exposure to yet. We have an excellent session on embedded FPGA that includes presentations from some of the leaders in this new market: Achronix, Flex Logix and Menta. They will talk about three very different ways of implementing FPGA as an IP which can be instantiated into an SoC, as opposed to the other way around (like Xilinx’s Zynq or Intel/Altera’s SoC FPGA line). Embedded FPGAs used to be a tough sell because FPGAs traditionally required a great deal of area, but eFPGA vendors are getting traction now with these new offerings which are purpose-built products for embedding in SoCs, rather than being derived from existing full chip FPGAs. I’m interested to find out what has made it possible for these vendors to go from “it’ll never work” to “yes, we have customers.” In fact, Flex Logix will have Sandia Labs, a customer, co-present and describe the end application which takes advantage of the reprogrammability of the eFPGA.

Another session I’m personally interested in deals with IP to support CMOS image sensors (CIS). The CIS market is exploding, and image sensors are being integrated in SoCs for multiple applications, including automotive. These new image sensor IPs require new architectures and also innovative mixed-signal design. Chronocam, Austria Micro Systems and Forza Silicon will each present their solutions in this space on Tuesday morning.

At the conference this year, we have an excellent mix of EDA, IP, SoC, and foundry process engineers who will talk about how our industry is changing. This is going to be a great year for DAC. The event is back in San Francisco again this year, so it’s an easy hop from Silicon Valley, just grab the bus and come on up!  I look forward to seeing you in June in San Francisco (June 24-28)!   Register today for the Designer and IP track badge. 

By Valeria Bertacco, 55^th DAC Conference Program Chair

This June at DAC, we will have the opportunity to discuss and learn about key topics that are emerging in the system design and automation community.

To start, we have the challenge of designing at the end of silicon scaling and beyond: devices, design complexity and verification. On Monday, there will be a tutorial on designing at advanced technology nodes, followed by an invited session on the same topic on Tuesday in the Designer Track.

We will also begin to discuss modern challenges in verification in the face of today’s design complexities. This hot topic will pick up throughout the week with panels, special sessions and reviewed paper presentations, ranging from automating away the complexity of the design process (“the road to no human in the loop” on Tuesday), design productivity (“design productivity in SoC,”  “mind the gap”), verification challenges (“black art of verification”) and new emerging devices (“the zoo of emerging devices”) to design tomorrow’s computing systems.

For those of you  interested in emerging storage and storage technologies, there is also abundant coverage:  From solid-state storage devices (“how solid is your storage,” “solid ideas”), to the storage-centric system solutions (“memory-centric architectures,” “emerging storage,” “memory that never forgets”), complemented by a thorough discussion of the leeway of approximation techniques, in particular in relation to their impact on storage, system reliability and application accuracy (“watch your bits,” “good enough is enough”).

For the researchers, both from industry and academia, we will have a two-hours panel on research funding. Wednesday after lunch we can discuss trends and directions in funding with a slate of panelists from around the globe. This topic is becoming a strong DAC tradition, in light of the interest it has attracted in the recent past.

Moreover, this year at DAC we will begin the conversation about diversity in our industry: what is its value, how do we attain a diverse work environment and what changes do we need to pursue for it to be effective. This discussion will start with an all-day Monday tutorial and will continue with a panel on Wednesday afternoon (“making your team high performing,” “diverse engineering teams are better”).

And then, we have of course the two topics that have been gaining the strongest momentum in the past few DAC events: security and deep learning. On the security front, the program offers two tutorials on “IoT security” and “verification for security.” Once we have built the background knowledge, the program offers multiple sessions each day, discussing software and hardware security, ranging from “best practices” in the designer track, to innovative solutions, both at the architectural and logic levels, in the context of general and embedded systems, particularly the highly exposed IoT world.

As you probably guessed, deep learning is pervasive throughout the program, and I cannot even begin to list all the sessions that tackle this topic. Just know that we will offer several research presentations, invited sessions and panels, both in the research and designer/IP tracks, presenting how to design for deep learning application systems, and how to leverage deep learning in our design processes; deep learning for security and security in deep learning applications. If you are not a deep learning expert, I strongly recommend the broad offering of tutorials (“ML for EDA,” “ML in IoT,” “data science for verification”) to get you up to speed by Monday night.

As you can see, it’s a packed conference program! I hope you will enjoy it, and find some time for the always important networking, too — at the sessions or at the research lounge. I will be there, walking the hallways and attending the talks, and I am very much looking forward to reconnect with old friends and meet the new faces of DAC!