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Posts Tagged ‘Verification’

Check out what DAC has in store for you!

Monday, January 25th, 2016

Chuck Alpert, General Chair of the 53rd DAC was recently interviewed by Warren Savage on Take Five.  Check out what DAC has in store this upcoming June and learn how you can still participate in the DAC program!


Experience the DVContinuum

Friday, May 15th, 2015

What’s the DVContinuum?

For more than 25 years, DVCon is the premier conference to discuss challenges and achievements for Functional Design and Verification of Electronic Systems and Integrated Circuits. The DVContinuum includes the well-established DVCon United States in March, augmented with DVCon India in September and DVCon Europe in November (Munich, Nov 11 – 12, 2015).

For each region, DVCon provides a well-chosen mixture of technical paper sessions, tutorials, key notes, posters and exhibits. Sponsored by Accellera Systems Initiative, DVCon attendees get access to the latest information on various Accellera Standards and its application for system-level design, modelling and verification (including UVM, SystemC, SystemVerilog, IP-XACT and many more). The topics include system-level virtual prototyping, IP reuse, design automation, mixed-signal design, low power design and verification. Facilitating DVCon not only in the US but also in Asia and Europe allow networking and discussions in a much broader audience and expand DVCon’s value to wider community than those only who have the opportunity to travel to the US.

If you like to share your experience with the DVContinuum, submit your paper: DVCon Europe deadlines are May 11th for your draft paper and June 1st for your Tutorial submission. More info: (India: US: )

The DVContinuum Anno 2015 – a Historic Perspective

As DVCon attendee, you will hear a lot about “shift left” and early verification of complex systems. This is not a new concept at all, even it may look like today. A very epic example for a historic shift left had been called out by John F Kennedy in May 1961: “I believe that this nation should commit itself to achieving the goal, before this decade is out, of landing a man on the moon and returning him safely to the earth.” At that time, the required technologies and procedures for a moon landing did not even exist.


Survivor’s Guide to Hardware Emulation at DAC

Tuesday, May 27th, 2014

It wasn’t all that long ago when hardware emulation providers heading to DAC worked overtime to get their booths filled with interested verification engineers with big challenges. Hardware emulation was still viewed as an esoteric and expensive luxury that only few could afford.

Fast forward to 2014. This year is prime time for hardware emulation, now a mandatory verification approach for all semiconductor designs. Left alone are a few analog-centric designs and a bunch of small digital designs. It is also become somewhat more affordable based on the price per gate.

I predict this year DAC will be much different than previous years as semiconductor companies, forced to accelerate time to market even as their chip designs get increasingly more complex, are looking to hardware emulation.


Using Formal Tools to Improve the Productivity of Verification at STMicroelectronics

Tuesday, April 9th, 2013

At this year’s ChipEx, STMicroelectronics (ST) will discuss how they used formal methods as a means to improve the productivity of their verification. In particular, they had three key aims:

  1. To close verification projects with appreciably less time and effort than that required by a constrained random approach;
  2. To promote a greater use of assertions by encouraging designers to develop formal properties for their blocks;
  3. To augment or replace legacy in-house flows with mature industry tools. This reduces maintenance overhead and promotes a more robust approach.

They applied formal methods at the unit-level, block-level and the system-level of an ARM based CPU sub-system (see Figure 1). Each project gave different insights into the effectiveness of the formal approach. In order to make an effective evaluation, they developed constrained random alternatives. This allowed them to make direct comparisons and reduced the project’s risk.

A paper at ChipEx will be presented that describes the productivity improvements they experienced using formal methods to verify a critical CPU sub-system that is targeted at mobile applications. In particular, they describe the challenges involved and how a formal tool (Jasper) delivered benefits in terms of effort savings, re-use and insight into IP that was not fully characterized in the context of a new design. The full presentation will also describe their experiences using formal in the context of low-power verification, control status register checking and sequential equivalence.

Figure 1: An ST ARM based CPU sub-system. The shaded blocks were verified using Jasper.


Get Powered Up with Formal Low Power Verification!

Monday, March 11th, 2013

We as consumers want more functionality from our electronic devices whether from our smart phones or household appliances.  The problem that we create from these functionality demands is not only an increase in power consumption, but also a significant increase in complexity for how the power in these devices is managed.  We as consumers don’t often think about these consequences, but your typical electronic design engineer certainly does.

Today’s electronic designs require that power management and reduction be a central concern throughout the chip design flow from architectural design to RTL implementation and physical design.  The power verification dilemma is two-fold.  Not only must the design and verification engineer address whether or not the inserted power management circuitry functions correctly, but also that the overall chip functionality is not corrupted by the power intent described in the UPF or CPF descriptions.


Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

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