Guest Blogger 
Matthieu Wipliez
Matthieu Wipliez is CTO and co-founder of the Synflow EDA start-up company. He has spent the last two years working on a new programming language called C~ ("C flow") for next-generation hardware design, and developing an IDE for that language. Matthieu writes about what he loves, like disruptive … More » Human-readable RTL code generationOctober 10th, 2013 by Matthieu Wipliez
Every now and then I meet somebody (compiler writers most of the time, but not only) who believes that generating human-readable RTL code is worthless. They claim that nobody should need to look at generated code, among other things because they should just trust the compiler, like software engineers do. It is time to examine the facts. 1. The majority of the hardware engineers that we’ve met with Synflow want to be able to understand the generated RTL, because they want to be able to reuse, verify, optimize or modify the generated code themselves. This includes people from big companies such as STMicroelectronics, Samsung, Renesas, ARM, as well as medium enterprises like Thomson Video Networks, RivieraWaves, ScaleoChip. Although this is only a subset of all hardware designers and semiconductor companies, I think we can consider it a reasonably representative sample. As a matter of fact, the rest of designers may not care whether the generated code is human-readable, but no designer has ever told us that he or she would prefer incomprehensible code, or even worse a netlist. Actually, that is probably because… Read the rest of Human-readable RTL code generation Come Back to the Future – EDA Style!September 25th, 2013 by Rob van Blommestein
“Sold! To…” Is a phrase we expect to hear a lot on the evening of October 16th. That’s the date when we celebrate the past 50+ years of EDA at the EDA: Back to the Future industry reunion hosted by EDAC. Why do we expect to hear this phrase a lot you ask? Well, part of the festivities will include silent and live auctions that will help raise money for the Computer History Museum’s EDA Oral Histories Collection and Exhibit. We want to capture and preserve our rich history of EDA. There will be items to bid on for every taste and budget. You could be the one to win a lunch with Aart or go home with a case of private reserve wine. Maybe you’re a sports fan. If so, then a private tour of AT&T Park, an autographed baseball from Giants Brandon Belt, or a round of golf with three of your closest friends is more up your alley. Are you a “foodie”? Well, how about dinner at some of Mountain View’s finest eateries? This event offers more than just a chance to walk away with something tangible. You’ll be able to mingle and dine with industry luminaries – the who’s who in EDA’s past, present, and future. What other event brings everyone together like that? And what event would be complete without some laughs and a little mystery? To find out what I mean, you’ll need to come. So get those bidding paddles ready and register to attend the must-be-at event in EDA. – http://www.edac.org/events/back_to_the_future Bitcoin mining IP core with Synflow StudioSeptember 15th, 2013 by Matthieu Wipliez
To design an ASIC Bitcoin miner, the first thing you will need is a Bitcoin IP core, a piece of silicon that performs a double SHA-256 (if the previous sentence is Klingon to you, I’d advise you to read the gentle introduction to Bitcoin mining). You can buy a SHA-256 IP from numerous IP vendors on the net, you can also find one free of charge on OpenCores. Or you can design one yourself. If you are aware of what’s wrong with RTL, or you know that High-Level Synthesis might not help you much, or you are an innovator, and/or simply you just want to see what Synflow Studio can do, keep reading!
Addressing the Challenges with SoC Integration and VerificationJune 20th, 2013 by Oz Levia
As a society entrenched in connectivity, we put a great deal of pressure on our portable electronic devices to provide us with more and more computing power and capabilities. Take this blog for example. As I’m traveling, I’m actually writing this blog post on my smart phone. To write this effectively, I need to be able to easily flip back and forth between PowerPoint, Word, and the Internet while still answering emails and the occasional phone call. The fact that my mobile device is able to handle all of these requests with no errors is astonishing given that just a few short years ago, this idea was just “pie in the sky”. The computation complexities that make this possible are staggering. But what is also staggering, is that even more complex designs are being created in ever shrinking time-to-market windows. How do system and SOC companies remain competitive with these seemingly unrealistic expectations? There are, of course, a myriad of answers to that question, but a critical facet is the use of third-party IP. More and more companies must adopt third-party IP so that they can focus their design on their companies’ core competence. Outsourcing other, proven, capabilities to IP providers saves a great deal of time, energy, and money. However, the use of this third-party IP also introduces new challenges for interface specification, integration, and verification of SoCs on a large scale. These challenges, if not addressed properly, can eliminate any of the productivity gains thought to be realized with the use of third-party IP. Read the rest of Addressing the Challenges with SoC Integration and Verification TSMC Ecosystem Moving OnlineJune 13th, 2013 by Tom Quan
There has been a great proliferation in the quantity and quality of online resources for IC designers over the past two decades. This expanding set of options benefits both the designers and ecosystem partners such as foundries, tool vendors and IP suppliers. For intellectual property (IP), multiple established sites deliver IP cataloging, news, planning and aggregation, and consulting. These useful services come from established providers like ChipEstimate, Design & Reuse, and Silicon-IP. Providing fast access to detailed information on thousands of IP alternatives helps build the market for IP innovators while providing designers with myriad technology solutions. Web-based EDA solutions are also becoming more mainstream. Many are ideally suited to the advantages that only online resources can deliver. Examples include Cadence’s hosted design solution, Mentor’s thermal analysis, Synopsys’ logic verification and Nimbic’s electromagnetic analysis. With seemingly unlimited compute power residing “in the cloud,” designers can have on-demand access to these types of scalable tools, eliminating constraints on their productivity. Using Formal Tools to Improve the Productivity of Verification at STMicroelectronicsApril 9th, 2013 by Rob van Blommestein
At this year’s ChipEx, STMicroelectronics (ST) will discuss how they used formal methods as a means to improve the productivity of their verification. In particular, they had three key aims:
They applied formal methods at the unit-level, block-level and the system-level of an ARM based CPU sub-system (see Figure 1). Each project gave different insights into the effectiveness of the formal approach. In order to make an effective evaluation, they developed constrained random alternatives. This allowed them to make direct comparisons and reduced the project’s risk. A paper at ChipEx will be presented that describes the productivity improvements they experienced using formal methods to verify a critical CPU sub-system that is targeted at mobile applications. In particular, they describe the challenges involved and how a formal tool (Jasper) delivered benefits in terms of effort savings, re-use and insight into IP that was not fully characterized in the context of a new design. The full presentation will also describe their experiences using formal in the context of low-power verification, control status register checking and sequential equivalence.  Figure 1: An ST ARM based CPU sub-system. The shaded blocks were verified using Jasper. Get Powered Up with Formal Low Power Verification!March 11th, 2013 by Rob van Blommestein
We as consumers want more functionality from our electronic devices whether from our smart phones or household appliances. The problem that we create from these functionality demands is not only an increase in power consumption, but also a significant increase in complexity for how the power in these devices is managed. We as consumers don’t often think about these consequences, but your typical electronic design engineer certainly does. Today’s electronic designs require that power management and reduction be a central concern throughout the chip design flow from architectural design to RTL implementation and physical design. The power verification dilemma is two-fold. Not only must the design and verification engineer address whether or not the inserted power management circuitry functions correctly, but also that the overall chip functionality is not corrupted by the power intent described in the UPF or CPF descriptions. Read the rest of Get Powered Up with Formal Low Power Verification! Silicon Valley veterans and experts accept young engineers as one of their own, at DesignCon, make them feel at homeFebruary 5th, 2013 by Shachi Nandan Kakkar
When I, a high school senior, got an invite to be a panelist at a panel discussion on “Engineering The Next Generation”, I was a bit surprised. I aspire to be an electronics or a computer engineer, but have still not entered College. My dad, Sunil Kakkar who founded a chip design and verification company SKAK Inc., serves on the technical program committee of DesignCon, told me that electronic design and semiconductor experts from all over the world will come to participate in the conference that will run for 4 days. The conference would be a high tech affair, so I would have to be technical in presenting my thoughts. I was somewhat apprehensive. Will he be able to get their attention – I thought? Could I speak on topics which will make sense to them? What will their reaction be, on a high school senior fromCupertinoHigh Schoolparticipating in the DesignCon conference? Oscillating microscopic beads could be key to biolab on a chipSeptember 25th, 2012 by Sanjay Gangal
Written by David Chandler, MIT News Office MIT team finds way to manipulate and measure magnetic particles without contact, potentially enabling multiple medical tests on a tiny device. If you throw a ball underwater, you’ll find that the smaller it is, the faster it moves: A larger cross-section greatly increases the water’s resistance. Now, a team of MIT researchers has figured out a way to use this basic principle, on a microscopic scale, to carry out biomedical tests that could eventually lead to fast, compact and versatile medical-testing devices. The results, based on work by graduate student Elizabeth Rapoport and assistant professor Geoffrey Beach, of MIT’s Department of Materials Science and Engineering (DMSE), are described in a paper published in the journal Lab on a Chip. MIT graduate student Daniel Montana ’11 also contributed to the research as an undergraduate.
Read the rest of Oscillating microscopic beads could be key to biolab on a chip The Concurrent Design-Flow ExperimentAugust 8th, 2012 by David Murray
At DAC this year I had a lot of fun doing a live experiment to demonstrate some of the benefits and issues with concurrent design flows. I was at the Cadence Theatre doing a presentation called ‘Controlling the costs of SoC integration‘ and I decided to make the presentation more interactive by creating a design team and seeing some of the effects of getting this team to work concurrently. We demonstrated how a little ‘twist’ caused a big upset for to team deliveries! Concurrency The topic I introduced first was how system design flows are now highly concurrent. In the production of a system within a very tight timescale, it would be normal to have architecture definition, software development, virtual prototype development, RTL design and verification all happening at the same time, be it IP, sub-system or SoC level design. I represented this as a set of rotating, interacting cogs. |
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