Reportedly, the latest update on the U.S.-China tech fight is China’s decision to place exports restriction on gallium and germanium, which – according to some observers – could be followed by restrictions on rare earth exports. As for semiconductor subsidies updates, Broadcom will reportedly invest in a European Union-funded program in Spain which would include the construction of “large-scale back-end semiconductors facilities unique in Europe.” And French research institute CEA will receive funding from the French government for the construction of a new fab in Grenoble with the goal of downscaling FD-SOI (fully depleted silicon on insulator) chips below 10-nanometer and a to develop a new generation non-volatile onboard memory.

Samsung Foundry roadmap updates

On occasion of its recent Samsung Foundry Forum in San Jose, the South Korean company announced it will begin mass production of the 2-nanometer process for mobile applications in 2025, and then expand to HPC in 2026 and automotive in 2027. Mass production of SF1.4 will begin in 2027 as planned. From 2025, Samsung will begin foundry services for 8-inch gallium nitride power semiconductors. The 5-nanometer radio frequency process is also under development and will be available in the first half of 2025. Samsung Foundry is adding new manufacturing lines in Pyeongtaek, South Korea, and Taylor, Texas. The company said the construction of the new fab in Taylor is proceeding according to initial plans and is expected to finish by the end of the year, beginning operation in the second half of 2024. Among other news, Samsung is launching its ‘Multi-Die Integration Alliance’ in collaboration with partner companies and players in memory, substrate packaging, and testing. The MDI Alliance aims to create a packaging technology ecosystem for 2.5D and 3D heterogeneous integration.

Read the rest of Samsung Foundry EDA tool certifications; AMD’s new emulation FPGA; AMD gaining ground in AI training

A fund backed by the Japanese government has reportedly agreed to buy Japanese photoresists supplier JSR. The deal would represent an additional effort of the Japanese government to revitalize its domestic semiconductor industry. Among the other interesting news this week, Intel implicitly admitting (in this press release) that it is currently spending up to $1.5 billion per year due to operational inefficiencies that its competitors don’t have. This refers to expedited wafers and test times, as explained below.

Intel to adopt an internal “fabless-foundry” model

Intel will adopt a new operating model where its internal product groups will move to a foundry-style relationship with the company’s manufacturing group. In this new “internal foundry” model, Intel’s product business units will engage with the company’s manufacturing group in a similar fashion that fabless semiconductor companies engage with external foundries. Intel’s manufacturing groups will be accountable to a standalone profit and loss (P&L) for the first time. The company expects this change to boost efficiency and therefore deliver significant cost savings. One example concerns “expedited” wafers that business units decide to move through Intel’s manufacturing process, which are costly and reduce factory efficiency. Going forward, this service charge will be borne by the business units, and it’s expected that it will reduce the number of expedites “to be on par with the competition”. Another example concerns Intel’s test times, which currently run “double or triple those of competitors”. As business units are charged market prices based on test time, Intel expects pre-silicon design choices to reduce these test times.

Read the rest of Intel’s new operating model; investments in India; Stellantis-Foxconn JV; a 51.2 Tbps SerDes

In view of its upcoming IPO, Arm is reportedly looking for some “anchor investors” among its main customers and end users. Companies in talks with Arm include Intel, Alphabet, Apple, Microsoft, TSMC, and Samsung. Let’s now move to this week’s news roundup, which mostly concerns EDA and IP. Among the other news, AMD disclosing details about its artificial intelligence products and strategy.

RF EDA updates: Keysight, Xpeedic

Keysight has introduced a new release of its PathWave Advanced Design System. The ADS 2024 suite offers new millimeter wave and subterahertz frequency capabilities targeting 5G and future 6G chips. According to Keysight, 3D electromagnetic analysis can be accelerated thanks to next-generation solvers, application-aware meshing algorithms, and an innovative circuit co-design and simulation approach. Increased circuit designer productivity is achieved through enhancements to the RFPro tool, which streamlines monolithic microwave integrated circuit and module workflows. Performance for microwave power amplifier designs can also be improved thanks to electrothermal simulation, signal modulation, and analysis capabilities. Xpeedic, too, has recently unveiled a new edition of its RF EDA solution. Innovations concern XDS, Xpeedic’s RF system-level design and simulation platform; IRIS, its on-chip passive modeling and simulation tool; and iModeler, a passive model generation tool.

Read the rest of RF EDA updates; Samsung Foundry-IP vendors agreements; AMD’s AI products and strategy; Intel planning new EMEA facilities

Updates concerning automotive applications make up a significant part of this week’s news roundup. Among the other themes, backside power delivery is getting closer to real-life applications; and more subsidies are going to benefit the European semiconductor ecosystem.

More European subsidies

In addition to the EU Chips Act, the European Union and some individual member States are going to provide more subsidies to their domestic semiconductor ecosystem. The European Commission has approved an “Important Project of Common European Interest” (‘IPCEI’) to support research, innovation and the first industrial deployment of microelectronics and communication technologies across the value chain. Fourteen member States will provide up to €8.1 billion in public funding, which is expected to unlock additional €13.7 billion in private investments. As part of this IPCEI, 56 companies, including small and medium-sized enterprises and start-ups, will undertake 68 projects.

Source: European Commission

Separately, the French government has announced it will provide 2.9 billion euros ($3.10 billion) in state aid to help support an investment of 7.5 billion euros that STMicroelectronics and GlobalFoundries are making to build a semiconductor factory in Crolles, France.

Read the rest of More semi subsidies; Intel’s BPD advancements; qualities of GeSn alloy; EV charging defacto standard

Open-source software for an open-source ISA: the Risc-V Software Ecosystem (RISE) Project is a new initiative dedicated to enabling a software ecosystem for application processors that includes software development tools, virtualization support, language runtimes, Linux distribution integration, and system firmware, working upstream first with existing open-source communities in accordance with open-source best practices. The RISE Governing Board includes Andes, Google, Intel, Imagination, MediaTek, Nvidia, Qualcomm, Red Hat, Rivos, Samsung, SiFive, T-Head, and Ventana.

New Arm mobile computing platform

At the recent Computex event in Taiwan, Arm announced its Total Compute Solutions 2023 (TCS23), a new platform for mobile computing aimed at premium smartphones. TCS23 IP includes a new Arm Immortalis GPU based on the 5th Generation GPU architecture, a new cluster of Armv9 CPUs supporting artificial intelligence, and other enhancements. A new graphics feature introduced in the 5th Gen GPU architecture is Deferred Vertex Shading (DVS), a technique that redefines the dataflow and enables partners to scale for larger core counts and higher performance points. A key part of the CPU cluster is the new Arm Cortex-X4 – “the fastest CPU that we have ever built,” Arm stated in a blog post – bringing 15 percent more performance compared to the Cortex-X3 while consuming 40 percent less power on the same process. Arm is taping out the Cortex-X4 on the TSMC N3E process.

Cadence will support customers using the new Arm TCS23 through RTL-to-GDS digital flow Rapid Adoption Kits (RAKs) for 3nm and 5nm nodes. The company has fine-tuned its RAKs for Arm Cortex-X4, Cortex-A720 and Cortex-A520 CPUs and Immortalis-G720, Mali-G720 and Mali-G620 GPUs. Cadence verification flow has also been optimized for the newest Arm CPUs and GPUs.

Synopsys, too, has announced support for TCS23 through QuickStart Implementation Kits (QIKs) that are tuned for the latest 5, 4 and 3nm process technologies.

Read the rest of Arm’s TCS23; AI partnerships; nickel aluminide; DVFS vulnerability; Cadence acquires Pulsic

According to Reuters, Nvidia is close to becoming the first trillion-dollar chip firm after its stock price increased about 25%, taking the company value to nearly $945 billion. The steep increase happened after Nvidia reportedly projected a quarterly revenue more than 50% above the average Wall Street estimate. “A trillion dollars of installed global data center infrastructure will transition from general purpose to accelerated computing as companies race to apply generative AI into every product, service and business process. (…) We are significantly increasing our supply to meet surging demand for them,” said Nvidia CEO Jensen Huang in a press release announcing the company’s latest financial results.

AI Generated Silicon Design Challenge

And one of the processes to which generative AI could be applied is chip design, at least according to Efabless which has just announced its “AI Generated Open-Source Silicon Design Challenge”. According to the company, Generative AI offers the potential to revolutionize chip design by automating many of the time-consuming tasks involved in the process. In this challenge, participants will use generative AI (e.g. chatGPT, Bard or similar) to generate Verilog from natural language prompts. Here’s a video example. The designs will then be implemented using the Efabless chipIgnite platform, which includes an SoC template (Caravel) providing rapid chip-level integration, and an open-source RTL-to-GDS digital design flow (OpenLane). Efabless intends to manufacture at least three winning designs.

Read the rest of Nvidia approaching trillion-dollar valuation; Applied Materials’ “world’s largest” semi R&D facility; new Intel AI processors

Competition heats up for processors aimed at cloud computing. Ampere (Santa Clara, CA) has just introduced a new family of what it calls “cloud native processors”, with 192 custom designed Ampere cores and a number of features aimed at cloud usages like AI. More news this week include innovations from both industry and academia.

New fab investments: Analog Devices in Europe, Micron in Japan

Analog Devices will invest €630 million at its European regional headquarters in Limerick, Ireland, to build a new 45,000 sq-ft R&D and manufacturing facility which will focus on signal processing innovations. The new facility is expected to triple ADI’s European wafer production capacity. The investment is planned as part of a collaboration within the European Union’s Important Projects of Common European Interest on Microelectronics and Communication Technologies (IPCEI ME/CT) initiative, and is supported by the Irish Government. One year ago, Analog Devices announced a separate investment of €100 million in “ADI Catalyst” at its Limerick campus. Ireland is also home to ADI’s main European Research and Development Center.

Micron Technology will be introducing EUV lithography to its Hiroshima (Japan) fab, to manufacture its next generation of DRAM, the 1-gamma (1γ) node. The company expects to ramp EUV into production on the 1-gamma node in Japan (as well as in Taiwan) from 2025 onwards. Micron will be the first semiconductor company to bring EUV technology to Japan for production, and expects to invest up to 500 billion yen in 1-gamma process technology over the next few years, with close support from the Japanese government.

Read the rest of Fab investments; silicon vs WBG materials; compressing simulation code; Ansys acquires Diakopto

EDA research is alive: the DAC 2023 technical program received a record high number of submissions. For the Research Track, the Conference’s Technical Program Committee reviewed 1,156 submitted research manuscripts and accepted 263 for presentation and publication. In addition, 269 Engineering Track submissions were reviewed with 71 accepted for presentation.

Hyperscalers updates: Microsoft, Meta, Google

Microsoft and AMD are reportedly collaborating on artificial intelligence chips. Unlike what one would expect, the AI processor design is being provided by Microsoft, not by AMD: it is the Athena chip that was in the news a couple of weeks ago. Microsoft is also reportedly providing financial support to bolster AMD’s AI efforts.

Meta (Facebook) has reportedly hired an Oslo-based team (at least ten engineers) that until late last year was building artificial-intelligence networking technology at British AI chip unicorn Graphcore. According to Reuters, Graphcore closed its Oslo office as part of a broader restructuring announced in October last year.

Among the many innovations introduced on occasion of the recent Google I/O event, Google Cloud has announced the private preview launch of the next-generation A3 GPU supercomputer for training and inference of generative AI and large language models. The A3 VMs combine Nvidia H100 Tensor Core GPUs and Google’s custom-designed 200 Gbps IPUs, with GPU-to-GPU data transfers bypassing the CPU host and flowing over separate interfaces from other VM networks and data traffic. This enables up to 10x more network bandwidth compared to Google’s A2 VMs. The A3 supercomputer’s scale provides up to 26 exaFlops of AI performance.

Read the rest of Microsoft-AMD collaboration; Google’s new cloud platform; memory price to decline; Synopsys acquires Silicon Frontline

Arm has officially started the process that will lead to its IPO on Nasdaq. As stated in a press release, the size and price range for the proposed offering have yet to be determined. Let’s now move to the rest of our weekly news roundup.

Market numbers: semiconductors 1Q2023, EDA 4Q2022

The chip market is slowing down. According to the Semiconductor Industry Association (SIA), worldwide sales of semiconductors totaled $119.5 billion during the first quarter of 2023, a decrease of 8.7% compared to the fourth quarter of 2022 and 21.3% less than the first quarter of 2022. Sales for the month of March 2023, however, increased 0.3% compared to February 2023. The EDA market, in contrast, is doing well. As recently announced by the ESD Alliance, Electronic System Design industry revenue increased 11.3% from $3,468.2 million in the fourth quarter of 2021 to $3,858.7 million in the fourth quarter of 2022.

Smartphone chipmakers seeking diversification

In terms of chip demand, one of the market segments that are suffering is smartphones, and this is having an impact on the leading smartphone chip suppliers. Qualcomm’s shares reportedly sank 7%, over the past few days, after the company signalled it would take longer for the smartphone market to rebound from a post-pandemic slump. Qualcomm, however, is diversifying towards automotive and IoT application, and its automotive revenue grew 20% from Q2 2022 to Q2 2023. A similar diversification strategy is being pursued by MediaTek: “We are definitely moving our resources very, very rapidly toward the automotive and computing area because those areas will provide our growth in the next three to five years in the future,” said MediaTek’s CEO Rick Tsai during the 1Q23 earnings call.

Read the rest of Digitally wrapped analog IP; 3D DRAM; CHIPS Act and EDA; Python acceleration

Catching up on some of the news from the past few weeks, let’s start by noting that yet another hyperscaler is developing its own AI chip: according to press reports, Microsoft is working on a device code-named Athena, currently being tested. Microsoft is reportedly accelerating the rollout following the success of ChatGPT.

Cadence leverages AI and the cloud to speed up PCB design

The new Cadence Allegro X AI technology promises to reduce the time for PCB placement and routing tasks from days to minutes, and with equivalent or higher quality compared with manually designed boards. Reduction in design turnaround time is achieved by automating placement, metal pouring and critical net routing – leveraging a scalable architecture that uses compute infrastructure on the cloud. Placement automation using generative AI enables feasibility analysis in the early phases of design. Exploring a much larger solution space than what is possible through manual methods, the technology drives optimization of metrics such as shorter wire lengths while adhering to the design constraints. Integration with signal integrity and power integrity analysis through the Allegro X Platform enables the user to optimize the designs for electrical and thermal performance. According to Cadence, the solution achieves a 10X or more reduction in PCB design turnaround time.

Read the rest of AI-based PCB design; SerDes and UCIe advancements; fully configurable Risc-V cores; Arm’s own silicon chip