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 EDACafe Editorial
Roberto Frazzoli
Roberto Frazzoli
Roberto Frazzoli is a contributing editor to EDACafe. His interests as a technology journalist focus on the semiconductor ecosystem in all its aspects. Roberto started covering electronics in 1987. His weekly contribution to EDACafe started in early 2019.

NeurIPS; advanced packaging; OCTRAM memory; graphene interconnect; Google’s quantum advancements

 
December 12th, 2024 by Roberto Frazzoli

Let’s start with a recent press leak: in a bid to win European Union approval of its Ansys acquisition, Synopsys has reportedly offered to sell its Optical Solutions Group to Keysight and also to divest Ansys PowerArtist.

Science meets AI at NeurIPS

Interestingly, artificial intelligence in its current form – which is based on neural networks – is probably the only example of a thriving industry built on a technology that does not have a clear, well defined scientific basis. Neural networks deliver amazing performance, spark the construction of gigantic datacenters, move enormous capitals – still, scientists don’t have a full grasp of what happens inside them. A workshop taking place at the NeurIPS conference – currently running in Vancouver – will address this topic. “While deep learning continues to achieve impressive results on an ever-growing range of tasks, our understanding of the principles underlying these successes remains largely limited,” the workshop organizers wrote in an abstract. “This problem is usually tackled from a mathematical point of view, aiming to prove rigorous theorems about optimization or generalization errors of standard algorithms, but so far they have been limited to overly-simplified settings.” According to these scientists, the “scientific method” in the study of neural networks “has been largely underexplored”. The scientific method, they explain, enables the “empirical analyses of deep networks that can validate or falsify existing theories and assumptions, or answer questions about the success or failure of these models.”

TSMC reportedly in talks for Nvidia Blackwell production in Arizona

TSMC is reportedly in discussions with Nvidia to produce the Blackwell AI chips at the foundry’s new plant in Arizona. Blackwell chips have so far been manufactured at TSMC’s facilities in Taiwan. However, even if produced in Arizona the chips will still need to be shipped to Taiwan for packaging, as the Arizona facility reportedly does not have CoWoS capacity.

Advanced packaging updates: Broadcom, QPT, YorChip/Digitho

Broadcom has announced the availability of its 3.5D eXtreme Dimension System in Package (XDSiP) technology for AI custom accelerators in consumer applications, where 3.5D means the combination of both 2.5D (placing chips side by side on an interposer) and 3D (chip stacking) in the same package. Another distinctive feature of the new solution – which is based on TSMC’s 2.5D CoWoS packaging technologies – is the face-to-face (F2F) chip stacking, directly connecting the top metal layers of the top and bottom dies. Broadcom’s lead F2F 3.5D custom accelerator integrates four compute dies, one I/O die, and six HBM modules.

Broadcom’s 3.5D package. Credit: Broadcom

UK-based QPT has developed a new die attach process for GaN power transistors which promises up to 15x better heat removal and greater reliability. According to the company, with the conventional approach the heat from the die has to pass through a thick sinter layer to reach the heat sink, which is placed on one side only. In contrast, QPT’s new structure is a sandwich that includes special ultrathin “qAttach” layers and heat sinks on both sides.

Credit: QPT

YorChip and Digitho are developing what they call “a breakthrough 2D low cost advanced chiplet packaging solution.” According to the two companies, currently advanced packaging is too expensive for mass market applications. As stated in the announcement press release, the technology has already been proven in MEMS market and eliminates expensive interposers. It is also expected to enable short reach connections of sub 1-millimeter, in turn allowing a smaller UCIe PHY size and lower power for data transmission.

Kioxia’s OCTRAM low power DRAM

At the recently held IEDM conference, Kioxia introduced OCTRAM (Oxide-Semiconductor Channel Transistor DRAM), a new type of 4F2 DRAM – developed in collaboration with Nanya – based on an oxide-semiconductor transistor that has both a high ON current, and an ultra-low OFF current. This technology is expected to realize a low power DRAM by leveraging the ultra-low leakage property of the InGaZnO (indium, gallium, zinc, oxygen) transistor.

Credit: Kioxia

Will graphene replace copper in interconnect?

Startup Destination 2D (Milpitas, CA) has successfully achieved wafer-scale synthesis of high-quality graphene within CMOS-compatible process conditions. According to the company, this achievement will enable the semiconductor industry to use graphene for the construction of interconnects in integrated circuits, thus replacing copper that is approaching its limits in advanced nodes because of its resistance. The main problem that Destination 2D addressed is that large area graphene synthesis, typically involving chemical vapor deposition (CVD) based techniques, requires high temperatures. Moreover, for interconnect applications multiple layers of edge-contacted graphene along with suitable “intercalation-doping” are required.

U.S. CHIPS Act updates

Here’s a quick update on some of the recent activities of the U.S. Department of Commerce concerning the CHIPS Act. Funding awarded: up to $75 million to Absolics (construction of a glass substrates facility in Covington, Georgia); up to $77 million to Entegris (construction of a manufacturing center in Colorado Springs for liquid filtration and FOUPs); up to $6.165 billion to Micron Technology (expansion of leading-edge DRAM production in Idaho and New York). Preliminary memoranda of terms: up to $33 million to Coherent (expansion and modernization of the company’s existing facility in Sherman, Texas, for indium phosphide devices); up to $16 million to SkyWater Technology Foundry (modernization of its existing facility in Bloomington, Minnesota); up to $50 million to X-Fab (expansion and modernization of its SiC foundry facility in Lubbock, Texas); up to $275 million to Micron Technology (expansion and modernization of a facility in Manassas, Virginia.)

Google’s quantum advancements

Google Quantum AI has announced Willow, its latest quantum chip. As stated in a company blog post, Willow has state-of-the-art performance across several metrics, enabling two major achievements. The first is that Willow can reduce errors exponentially as it scales up using more qubits. Google researchers explain that this achievement cracks a key challenge in quantum error correction that the field has pursued for almost thirty years. Second, Willow performed a certain benchmark computation – a standard for quantum research – in under five minutes, a task that would take one of today’s fastest supercomputers 10 septillion (that is, 1025) years.

New release of RS DesignSpark PCB software

RS has released a new version of its DesignSpark PCB software, introducing new features for both free and paid subscription plans.

Acquisitions

onsemi has entered into an agreement to acquire the SiC JFET technology business from Qorvo, including the United Silicon Carbide subsidiary, for $115 million in cash. Silicon Carbide Junction Field-Effect Transistors offer the lowest on-resistance per chip area and allow for the use of typical off-the-shelf drivers, the same used with silicon transistors.

Further reading

The U.S. Department of Commerce’s Bureau of Industry and Security (BIS) has released a 10-page report on U.S. companies’ use of legacy chips manufactured in China. Among the findings, companies that sell products containing legacy chips continue to lack visibility into their semiconductor supply chains. About half of surveyed companies were unable to determine whether their products contained any chips manufactured by China-based foundries.

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