Major news updates this week include the first insights into how US taxpayers’ money will be used to support the domestic semiconductor industry. Among the other updates, fast-charging car batteries getting closer to mass production.
Details of U.S. CHIPS Act implementation
The U.S. Department of Commerce has released its implementation strategy for the $50 billion CHIPS Act. The program, called ‘CHIPS for America’, will be housed within the National Institute of Standards and Technology (NIST). Approximately three quarters of the incentives funding, around $28 billion, will be targeted to establish domestic production of leading-edge logic and memory chips that require the most sophisticated manufacturing processes available today. Arguably, Intel and Micron will be the main beneficiaries of this share. At least a quarter of the available CHIPS incentives funding, or approximately $10 billion, will be devoted to new manufacturing capacity for mature and current-generation chips, new and specialty technologies, and for semiconductor industry suppliers. The remaining $11 billion will be invested in new R&D initiatives – a National Semiconductor Technology Center, a National Advanced Packaging Manufacturing Program, up to three new Manufacturing USA Institutes – and in NIST metrology R&D programs.
Some details about the conditions under which applicant companies will be granted ‘CHIPS for America’ funding have been provided by US Commerce Secretary Gina Raimondo during a press briefing at the White House. “This is not a blank check for companies,” she said. “This is not for them to pad their bottom line.” (…) “CHIPS funds cannot be used for stock buybacks. CHIPS funds are not intended to replace private capital,” she added. Raimondo then addressed issues specifically concerning China, explaining that beneficiary companies “are not allowed to use this money to invest in China, they can’t develop leading-edge technologies in China, they can’t send latest technology overseas.” (…) “Companies who receive CHIP funds can’t build leading-edge or advanced technology facilities in China for a period of 10 years. Companies who receive the money can only expand their mature node factories in China to serve the Chinese market,” she said.
More U.S. and western European tech companies have reportedly closed their Russian operations: among them Dell, Logitech, Ericsson and Nokia. Another significant update on geopolitical matters is the export ban on some Nvidia and AMD products (see below). However, the effectiveness of sanctions against China is a debated issue – see, for example, this EETimes article – and reverse engineering on a SMIC chip has provided additional surprises: TechInsights has found many similarities in process technologies, designs and innovations between SMIC’s 7-nanometer and TSMC’s 7-nanometer nodes. According to TechInsights, also, it is a notable achievement for SMIC having moved from 14-nanometer to 7-nanometer in just two years, without access to the most advanced western equipment and technologies.
Export restrictions on some advanced Nvidia GPUs and AMD accelerators
Nvidia and AMD have reportedly been told by the US government to halt exports of certain high-performance chips and systems to China. As for Nvidia, the restrictions cover A100 and forthcoming H100 GPUs, and any systems that include them, effective immediately. AMD has reportedly been given new requirements by the US Department of Commerce that will hit shipments of its MI250 accelerator to China. In a regulatory filing, Nvidia said that the export restrictions are due to a potential risk of the products being used by, or diverted to, a “military end user.” Both companies said the new mandate also covers a ban in export to Russia.
Catching up on some of the latest news after a summer break, two significant updates concern EDA as the subject of geopolitical tensions between China and the Western countries. More news in this week’s article includes new fab and packaging plant announcements – some of which spurred by the recently passed U.S. ‘CHIPS and Science Act’ – as well as updates concerning the processor market.
U.S. export controls on EDA tools for GAA transistor design
On August 12 the U.S. Commerce Department’s Bureau of Industry and Security issued a rule that establishes new export controls on four “emerging and foundational technologies” that are considered essential to the national security of the United States. Among them, two substrates of ultra-wide bandgap semiconductors – gallium oxide (Ga2O3) and diamond – and electronic CAD software specially designed for the development of integrated circuits with Gate-All Around Field-Effect Transistor structure.
Ban on GAA design tools a potential problem for China, says TrendForce
According to market research firm TrendForce, this new U.S. EDA software ban may actually affect China’s advanced IC design. The analysts observe that the three major U.S. EDA players (Synopsys, Cadence, and Siemens) account for a total 75% market share, and that Empyrean Technology – the leader of China’s EDA industry – has not yet touched upon GAA research and development. TrendForce also notes that even if China purchased a large amount of authorized EDA software before the current sanction takes effect, the United States could block its use by remotely denying license updates. In conclusion, according to TrendForce, without U.S. EDA tools, Chinese IC design – as well as Chinese foundries – will experience difficulties developing advanced 3-nanometer process design.
Catching up on some of the news from the last thirty days or so, several updates obviously concern U.S.-China tensions. As far as the semiconductor industry is concerned, news includes additional export restriction being considered by the U.S Government to halt China’s advances in semiconductor manufacturing, but the intricacies of a globalized ecosystem may cause side effects. According to analysts quoted by Reuters, export restrictions could also impact China-based memory fabs belonging to South Korean manufacturers such as Samsung and SK Hynix. A similar impact could be caused by export restrictions on European semiconductor equipment: for example – according to Reuters – the export ban has prevented SK Hynix from installing ASML’s EUV lithography equipment in its DRAM fab in Wuxi, China. Meanwhile, China’s IC sales keep increasing: according to market analysis firm TrendForce, the growth rate was 17% in 2020, 18.2% in 2021 and it is expected to be 11.21% in 2022.
Fab and foundry updates: SkyWater, Micron, ST-GlobalFoundries, IFS-MediaTek, Intel-TSMC
Also related to geopolitical tensions is the recent passing of the U.S. ‘Chips and Science Act’. Some companies have already announced their intentions to leverage this public funding measure: among them, U.S. foundry SkyWater plans to build a $1.8 billion semiconductor R&D and production facility in Indiana through a public-private partnership with the State and Purdue University; and U.S. memory maker Micron Technology intends to invest “in bringing the most innovative leading-edge memory manufacturing to the U.S.” More details regarding Micron’s plans are expected in the coming weeks.
The Design Automation Conference is back to its usual summer timeframe – again at the Moscone Center in San Francisco – with over one hundred exhibitors and a rich conference program that covers a wide range of topics including artificial intelligence, autonomous systems, Risc-V, security, embedded systems and more. Here we will briefly highlight some of the conference content more directly related to EDA, referring readers to the conference program for the detailed schedule.
EDA vendors’ top executives on stage: keynotes and panels
As usual, the DAC will offer attendees the opportunity to listen to EDA vendors’ top executives and – to some extent – to ask them questions. This year’s keynoters will include Anirudh Devgan, Cadence CEO, speaking about “Computational Software and the Future of Intelligent Electronic System Design”. More EDA executives will give speeches as part of a series called SKYTalks: Joe Sawicki from Siemens EDA (“Delivering ‘Smarter’ Faster: The Future of EDA & AI”), and Sandeep Mehndiratta from Synopsys (“It’s Getting Cloudy Out There”). Among the panels featuring EDA vendor executives, the top spot obviously goes to John Cooley’s DAC Troublemaker Panel, offering attendees the opportunity to hear “edgy questions” being asked to Joe Sawicki (Siemens EDA), Tom Beckley (Cadence), Dean Drako (IC Manage), Prakash Narain (Real Intent), Tony Chan Carusone (Alphawave IP) and Sam Appleton (Ausdia).
Quick updates on the impact of Ukraine war. Global exports of semiconductors to Russia have reportedly slumped by 90% due to export controls. And U.S. Commerce Secretary Gina Raimondo has reportedly threatened to “shut down” China’s SMIC foundry if it is found to be supplying chips to Russia. “We will shut them down and we can, because almost every chip in the world and in China is made using U.S. equipment and software,” she said. Moving to new fab updates, Taiwan’s GlobalWafers will reportedly invest $5 billion on a new plant in Sherman, Texas, to make 300-millimeter silicon wafers, switching to the United States after a failed investment on Germany’s Siltronic.
Samsung’s 3-nm GAA in production
Samsung Electronics has announced that it has started initial production of its 3-nanometer process node applying its Gate-All-Around (GAA) transistor architecture called Multi-Bridge-Channel FET (MBCFET), enabling a supply voltage reduction and a higher drive current capability. Initial applications are targeting high performance, low power computing, with plans to expand to mobile processors. According to the company, Samsung’s proprietary technology – which utilizes nanosheets with wider channels – allows higher performance and greater energy efficiency compared to GAA technologies using nanowires with narrower channels. However, channel width in Samsung’s 3nm GAA technology can be adjusted to obtain various power/performance combinations. Compared to 5nm process, Samsung claims that the first-generation 3nm process can reduce power consumption by up to 45%, improve performance by 23% and reduce area by 16%; the second-generation 3nm process is expected to reduce power consumption by up to 50%, improve performance by 30% and reduce area by 35%.
The so-called metaverse now has its standardization initiative: called Metaverse Standards Forum, it brings together a few dozen founding members including Meta (Facebook), Microsoft and Nvidia – but, as noted by Reuters, the member list currently does not include Apple. However, “the Forum is open to any company, standards organization, or university at no charge,” says the announcement press release, so never say never. Let’s now move to our usual news round-up, that this week includes a couple of interesting academic works.
Quick EDA updates
Keysight’s PathWave RFPro, integrated with the Synopsys Custom Compiler design environment, is enabled to support TSMC’s newest N6RF Design Reference Flow.
Pulsichas added new features to its Unity product. Among them, Unity Chip Planning technology now can handle incremental floorplans; and the embedded integrations with Cadence Virtuoso and Synopsys Custom Compiler allow users to access Unity directly from these systems.
Cadence’s Design IP offering has already achieved over twenty design wins in TSMC’s 5nm process technology, with multiple first-pass silicon successes.
Xpeedichas recently released its latest RF EDA/Filter Design Platform 2022.
Geopolitical issues keep making news: a team of U.S. investors, scientists, operators, and national security experts has founded America’s Frontier Fund (AFF), described as “the nation’s first non-profit strategic investment fund focused on building and scaling breakthrough deep-tech companies and platforms for the national interest.”. Led by CEO and co-founder Gilman Louie, AFF intends to counter “authoritarian nations” that “are committed to out-spending and out-innovating the U.S. to gain military and economic superiority.” The fund’s initial areas of focus will include microelectronics, artificial intelligence, new materials, quantum sciences, next generation networks (5G/6G), advanced manufacturing, and synthetic biology. Let’s now move to other news updates, this week with a significant presence of European research centers.
Imec demonstrates backside power delivery with buried power rails
Belgian research institute Imec has demonstrated a routing scheme for logic ICs with backside power delivery enabled through nano-through-silicon-vias (nTSVs) landing on buried power rails (BPRs). The BPRs connect to scaled FinFET devices whose performance was not impacted by backside wafer processing. The novel routing scheme with decoupled power and signal wiring acts as a scaling booster for future logic technologies (2nm and beyond), as the nTSVs land on BPRs with tight overlay control and are implemented at a tight pitch of 200nm without consuming any area of the standard cell. The solution also offers a system performance benefit by improving the power delivery, as it reduced IR voltage drop. Additionally, Imec demonstrated a performance boost by implementing a 2.5D MIMCAP (metal-insulator-metal capacitor) in the backside serving as a decoupling capacitor. Backside power delivery – using the back side of the wafer to route power lines, in order to alleviate routing congestion on the front side and reduce IR voltage drop – can be implemented in different ways; Imec believes that combining it with buried power rails is the most promising implementation scheme.
TEM image showing scaled FinFET devices connected to the wafer’s backside (through nTSVs and BPR) and frontside (through BPR, VBPR and MOA). Copyright: Imec
According to Reuters reports on the impact of Ukraine war, more U.S. tech companies are leaving Russia: Microsoft is substantially cutting its activity in the country, while IBM is closing its Russian business and has started to lay off its employees. Russia, for its part, has limited exports of noble gases including neon – used in chip fabrication – until the end of 2022. Exports will be allowed only with special State permission. Let’s now move to our usual tech news round-up, starting with a brief update on TSMC’s roadmap: the Taiwanese foundry has reportedly chosen the nanosheet transistor architecture for its next 2-nanometer node starting in 2025. As for EDA, the use of artificial intelligence/machine learning in chip design is in the spotlight this week with two significant announcements.
Synopsys has introducedDesignDash, a design optimization solution based on machine learning and big data analytics. According to the company, DesignDash enhances design productivity in different ways: by providing real-time design status through visualizations and interactive dashboards; deploying deep analytics and machine learning to extract and reveal actionable understanding from vast volumes of structured and unstructured EDA metrics and tool-flow data; classifying design trends, identifying design limitations, providing guided root-cause analysis and delivering flow consumable, prescriptive resolutions. The solution complements the Synopsys SiliconDash product, part of the Synopsys Silicon Lifecycle Management Family.
China is among the themes of this week’s roundup, with news concerning both its richly funded AI chip providers and – despite growing geopolitical tensions – its attractiveness for European investments.
Merck to build a new site in China
Germany-based Merck KGaA has reportedly signed a contract to open a base in the Chinese city of Zhangjiagang, describing it as its largest single electronics business investment in the country. In the new site, a 69-acre lot, Merck will build production facilities for thin film materials and electronic specialty gasses, along with a warehouse and operation centers. “China is currently the fastest growing semiconductor manufacturing market worldwide,” Merck China President Allan Gabor reportedly said in a statement. “We believe a golden era for China’s semiconductor industry has just begun,” he added.
Will Ukraine war accelerate transition to electric vehicles?
War in Ukraine is causing a shortage of wire harnesses – the complex and heavy cable bundles connecting all the electrical/electronics components of a vehicle – as the Eastern European country is a major supplier of these products. The shortage could accelerate transition from traditional vehicle network architectures based on “domain ECUs” to the new architectures based on “zonal ECUs”, which enable a dramatic simplification of vehicle wiring. This, at least, is the opinion of the industry experts quoted in a recent Reuters report. Simpler and lighter cable bundles would reduce carmakers dependence on Ukraine and other countries with a low labor cost, but their adoption would require redesigning the vehicles’ data and power networks. This could prompt a quicker phase-out of gasoline and diesel vehicles, as carmakers would rather not invest money in redesigning products that are approaching the end of their lives. Zonal ECUs are also paving the way to new wiring technologies such as the flexible circuits developed by CelLink (San Carlos, CA), already being used in ‘native’ electric cars.
