Roberto Frazzoli is a contributing editor to EDACafe and a seasoned freelance journalist specialized in electronics. His weekly contribution to EDACafe – since early 2019 - includes news updates, coverage of major industry events, special reports, and interviews. Prior to joining EDACafe, Roberto … More »
A quick look at the DAC 2022 conference program
July 8th, 2022 by Roberto Frazzoli
The Design Automation Conference is back to its usual summer timeframe – again at the Moscone Center in San Francisco – with over one hundred exhibitors and a rich conference program that covers a wide range of topics including artificial intelligence, autonomous systems, Risc-V, security, embedded systems and more. Here we will briefly highlight some of the conference content more directly related to EDA, referring readers to the conference program for the detailed schedule.
EDA vendors’ top executives on stage: keynotes and panels
As usual, the DAC will offer attendees the opportunity to listen to EDA vendors’ top executives and – to some extent – to ask them questions. This year’s keynoters will include Anirudh Devgan, Cadence CEO, speaking about “Computational Software and the Future of Intelligent Electronic System Design”. More EDA executives will give speeches as part of a series called SKYTalks: Joe Sawicki from Siemens EDA (“Delivering ‘Smarter’ Faster: The Future of EDA & AI”), and Sandeep Mehndiratta from Synopsys (“It’s Getting Cloudy Out There”). Among the panels featuring EDA vendor executives, the top spot obviously goes to John Cooley’s DAC Troublemaker Panel, offering attendees the opportunity to hear “edgy questions” being asked to Joe Sawicki (Siemens EDA), Tom Beckley (Cadence), Dean Drako (IC Manage), Prakash Narain (Real Intent), Tony Chan Carusone (Alphawave IP) and Sam Appleton (Ausdia).
Is EDA academic research moving to China?
Besides EDA vendors, the other pillar of the DAC is of course academic research – and a quick look at this year’s “Organizations” page is enough to get a sense of the growing role played by Chinese universities in this area. Top performer among Chinese academic organizations is probably Tsinghua University (Beijing) with sixteen presentations – mostly research manuscript – involving over sixty authors. Just compare this with the contributions from Stanford University (six presentations) or Berkeley University (five presentations). This reflects two trends highlighted by EDA veterans in a recent EDACafe special report: U.S. universities reducing the resources devoted to EDA research, and China investing huge amounts of money in EDA startups.
Machine learning in EDA, a ubiquitous theme
Not surprisingly, machine learning in EDA is a running theme in many DAC 2022 research papers, panels and presentations. Summarizing here all the ML-related conference content is therefore impossible; we will only highlight some of the relevant panels and sessions. Brian Bailey from Semiconductor Engineering will moderate “ML for Verification: Does it Work or Doesn’t It?”; presenters will include Clark Barrett (Stanford University), Erik Berg (Microsoft), Shobha Vasudevan (Google), Sandeep Srinivasan (VerifAI) and Avi Ziv (IBM). The session “Re-visioning what EDA can do for ML, and what ML can do for EDA” will feature presentations from Sicun (Sean) Gao (University of California, San Diego), Satrajit Chatterjee (Google), Siddhartha Nath (Nvidia) and Igor Markov (Facebook). Ruchir Puri from IBM will moderate “Machine Learning for Electronic Design Automation: Irrational Exuberance or the Dawn of a Golden age”; panelists will include Andrew Kahng (University of California, San Diego), Alberto Sangiovanni Vincentelli (University of California, Berkeley), Giovanni De Micheli (École Polytechnique Fédérale de Lausanne) and Gary Marcus (Robust.AI). At least one of these panelists – Alberto Sangiovanni Vincentelli – is a severe critic of ML in EDA, so the audience can expect a lively discussion.
More panels and presentations
Let’s now take a look at some of the other panels or presentations addressing EDA-related themes. Brian Bailey from Semiconductor Engineering will moderate “Those Darn Bugs! When Will They be Exterminated for Good?”; panelists will include Ashish Darbari (Axiomise), Mark Glasser (Cerebras), Ty Garibay (Mythic) and Larry Lapides (Imperas). Andrew Kahng from University of California, San Diego will serve as the moderator for “What is the Future for Open-Source EDA?”, featuring David Byrd (Blueyard Capital), Peter Gadfort (Army Research Labs), Noel Menezes (Intel), Chuck Alpert (Cadence) and Mamta Bansal (Qualcomm). Moderated by Frank Schirrmeister from Cadence, the panel “What can EDA and the Electronics Ecosystem Do for Greener Electronics to Save the Planet?” will see the participation of Dipti Vachani (Arm), Dharmesh Jani (Meta), Vojin Zivojnovich (Aggios), David Pellerin (Amazon Web Services) and Jennifer Huffstetler (Intel). Jason Cong from University of California, Los Angeles, will moderate “What are the big opportunities in the next renaissance of EDA?”; panelists will include Sankar Basu (NSF), Timothy Green (Semiconductor Research Corporation), Prith Banerjee (Ansys), Jan Rabaey (University of California, Berkeley), Tim Cheng (Hong Kong University of Science and Technology) and Jayanthi Pallinti (APD). Moderator Apurva Kalia from Tufts University will present “What is the role of the EDA community in future life science breakthroughs?”, with contributions from Lou Scheffer (HHMI), Jacob Beal (Raytheon Technologies), Kate Adamala (University of Minnesota) and Sameer Sonkusale (Tufts University). Moderated by Rob Aitken from Arm, the session “Creating Robust EDA and IP Ecosystems to Strengthen the Global Semiconductor Supply Chain” will feature presentations from Tom Beckley (Cadence), Michael Buehler-Garcia (Siemens EDA), Michael Campbell (Qualcomm), Rahul Goyal (Intel) and Bari Biswas (Synopsys). Nitin Dahad from embedded.com will moderate “Is Democratization of Chip Design Already Happening?”, with Alain Dargelas (RapidSilicon), Rob Mains (Chips Alliance), Rick O’Connor (Open Hardware Group), Mohamed Kassem (eFabless) and Vic Kulkarni (Silicon Integrative Initiative). Moderated by Martin Barnasconi from Accellera, the panel “AMS language standards for Design and Verification: Standing still or moving forward?” will feature panelists from IBM, Intel, NXP, Renesas and Qualcomm. Tom Lee from Stanford University will moderate “Automating Analog Layout – Has the time finally come?”, with Steven Burns (Intel), Elad Alon (University of California, Berkeley), Ting-Sheng Ku (Nvidia) and Weikai Sun (Synopsys). Moderated by Max Shulaker from MIT, the panel “Heterogeneous 3D or Monolithic 3D, Which Direction to Go?” will see the participation of Subramanian Iyer (University of California, Los Angeles), Sonia Leon (Intel), Gabriel Loh (AMD) and Subhasish Mitra (Stanford University).
Market and finance presentations
The investor community and attendees interested in the EDA market will probably focus on three analysts’ presentations, given by Richard Wawrzyniak from Semico Research (“Semiconductor Market Trends: Tying it all together for the Big Picture”), Charles Shi from Needham & Company (“EDA to Power Through Semiconductor Cycles”), and Jay Vleeschhouwer from Griffin Securities (“The State of EDA: A View from Wall Street”).
To finish with, a quick mention of one of the tutorials offered by this year’s DAC: organized by Mathilde Karsenti from Siemens EDA, “Hardware/Software Co-design with High-Level Synthesis” will show how a “wake word” detection algorithm – initially in a software-only form, running on a Risc-V core – can be compiled into accelerators described as synthesizable RTL, using HLS. The accelerator designs will then be taken through RTL synthesis and place and route.