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Roberto Frazzoli
Roberto Frazzoli
Roberto Frazzoli is a contributing editor to EDACafe and a seasoned freelance journalist specialized in electronics. His weekly contribution to EDACafe – since early 2019 - includes news updates, coverage of major industry events, special reports, and interviews. Prior to joining EDACafe, Roberto … More »

Geopolitical tensions; fab updates; reverse engineering surprises; interconnect updates; acquisitions

 
August 5th, 2022 by Roberto Frazzoli

Catching up on some of the news from the last thirty days or so, several updates obviously concern U.S.-China tensions. As far as the semiconductor industry is concerned, news includes additional export restriction being considered by the U.S Government to halt China’s advances in semiconductor manufacturing, but the intricacies of a globalized ecosystem may cause side effects. According to analysts quoted by Reuters, export restrictions could also impact China-based memory fabs belonging to South Korean manufacturers such as Samsung and SK Hynix. A similar impact could be caused by export restrictions on European semiconductor equipment: for example – according to Reuters – the export ban has prevented SK Hynix from installing ASML’s EUV lithography equipment in its DRAM fab in Wuxi, China. Meanwhile, China’s IC sales keep increasing: according to market analysis firm TrendForce, the growth rate was 17% in 2020, 18.2% in 2021 and it is expected to be 11.21% in 2022.

Fab and foundry updates: SkyWater, Micron, ST-GlobalFoundries, IFS-MediaTek, Intel-TSMC

Also related to geopolitical tensions is the recent passing of the U.S. ‘Chips and Science Act’. Some companies have already announced their intentions to leverage this public funding measure: among them, U.S. foundry SkyWater plans to build a $1.8 billion semiconductor R&D and production facility in Indiana through a public-private partnership with the State and Purdue University; and U.S. memory maker Micron Technology intends to invest “in bringing the most innovative leading-edge memory manufacturing to the U.S.” More details regarding Micron’s plans are expected in the coming weeks.

More fab updates – obviously unrelated to the U.S. Chips Act – are coming from Europe, where STMicroelectronics and GlobalFoundries have signed a Memorandum of Understanding to create a new, jointly-operated 300mm FD-SOI fab adjacent to ST’s existing 300mm facility in Crolles, France. This facility is targeted to ramp at full capacity by 2026, with up to 620,000 300mm wafer per year production at full build-out (~42% ST and ~58% GF).

In terms of foundry deals, MediaTek has signed a partnership to manufacture some of its chips using Intel Foundry Services. On the other hand – according to market research firm TrendForceIntel has delayed its orders to TSMC for the tile GPU chipset in Meteor Lake, and this incident has greatly affected TSMC’s production expansion plan for the 3-nanometer process.

SMIC’s 7-nanometer process

Canadian reverse engineering firm TechInsights has found a 7-nanometer process in a chip manufactured by Chinese foundry SMIC, the MinerVa Bitcoin Miner. This finding is considered surprising as – due to sanctions – SMIC does not have access to EUV equipment. However, TechInsights notes that “we saw multiple 7nm nodes from Samsung and TSMC in the past that did not require the use of EUV lithography, but this came at the cost of increased process complexity and design rule restrictions for the design libraries.” According to TechInsights, “this low-volume production product [the MinerVa Bitcoin Miner] may be the steppingstone for a true 7nm process that incorporates scaled logic and memory bitcells. (…) SMIC will not likely have [EUV lithography] in the near-to medium term and will continue to evolve the 7nm node without that capability, at the cost of increasing complexity (and resulting yield issues).” As reported by market analysis firm TrendForce, SMIC’s annual sales revenue in 2021 was US$5.44 billion, growing 39% year-on-year, and it posted net profit of US$1.775 billion, growing 147.76% year-on-year. In term of wafer size, 12-inch products contributed approximately 60% of SMIC’s revenue in the past year.

Some 4nm nodes looking identical to their 5nm predecessors

Reverse engineering analysis performed by TechInsights has provided more surprising findings, concerning 4-nanometer process nodes from both TSMC and Samsung – which analyst Linley Gwennap commented in a recent article (“Editorial: Nanometer Nonsense”). As for TSMC’s N4 node and its MediaTek early adopter, TechInsights “found the critical process dimensions were exactly the same as in TSMC’s earlier N5 products. The foundry’s claim of 4nm production was a sham, as was MediaTek’s claim of having a 4nm processor.” Gwennap wrote. Then “Qualcomm launched the Snapdragon 8 Gen 1 as a 4nm part on Samsung’s 4LPX process. After analyzing the Snapdragon chip, TechInsights found that 4LPX is no different than 5LPE,” he added.

Interconnect updates: Clock Domain Crossing, Bunch of Wires, CXL 3.0

Accellera has formed a Proposed Working Group (PWG) to focus on defining a standard Clock Domain Crossing (CDC) collateral specification to ease SoC integration. As explained in a press release, today SoC teams cannot reuse IP-level CDC collateral in the SoC environment if both teams use different CDC verification tools. This scenario is causing a CDC verification problem when the SoC teams source IP from providers that use a different tool for their own CDC verification. The PWG will provide a recommendation to start or not start a working group.

The Open Compute Project Foundation has released the ‘Bunch of Wires’ (BoW) specification for chiplet interconnect. BoW specifies a physical layer (PHY) optimized for System on a Chip disaggregation, and complements OCP ODSA Open High Bandwidth Interconnect (OpenHBI) PHY specification targeting High Bandwidth Memory and other parallel bandwidth intensive use cases.

As for datacenter connectivity, the CXL Consortium has released the CXL 3.0 specification, which expands on previous technology generations to increase scalability and to optimize system level flows with advanced switching and fabric capabilities, efficient peer-to-peer communications, and fine-grained resource sharing across multiple compute domains.

Acquisitions

Navitas, a U.S.-based manufacturer of gallium nitride power integrated circuits, has announced the acquisition of Belgium-based VDD Tech, a provider of digital isolators for power conversion.

Norway-based Nordic Semiconductor has entered into an agreement to acquire Mobile Semiconductor, a privately-held U.S. company specializing in embedded memory technology – such as ultra low power SRAM – for microcontrollers and Systems-on-Chip. Mobile Semiconductor has long provided the RAM memory used in all of Nordic’s wireless IoT devices.

Infineon has acquired NoBug Consulting SRL (Romania) and NoBug d.o.o. (Serbia). Founded in 1998, NoBug is a privately owned engineering company with approximately 120 engineers providing verification and design services for semiconductor products. The two NoBug sites will become Infineon’s R&D competence centers for its Connected Secure Systems (CSS) Division to work on complex IoT product developments.

Semtech (Camarillo, CA) will acquire Canada-based Sierra Wireless in an all-cash transaction representing a total enterprise value of approximately US$1.2 billion. Semtech expects the combination of Sierra Wireless’ cellular capabilities with Semtech’s LoRa-enabled end nodes to enable new IoT use cases. More synergies are expected from the combination of Sierra Wireless’ Cloud services offerings and Semtech’s LoRa Cloud services. Details of the deal can be found in this presentation.

A coverage of DAC panels and keynotes

Let’s finish by flagging some blog posts authored by Cadence’s Paul McLellan. One of them provides a transcript of John Cooley’s Troublemaker’s panel at the last DAC; the other ones summarize some analyst presentations and keynotes from DAC Day One, Day Two, and Day Three.

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