Will artificial intelligence ever be able to replicate biological brains? It’s a fact that research is advancing on all fronts. On the one hand, the semiconductor industry continues to push transistor size reduction – examples can also be found in some of this year’s IEDM papers – paving the way to systems comprising an ever larger number of transistors. On the other hand, scientists have started bridging artificial intelligence and neurosciences to explore overall network structures – as in recent research from Cambridge University – extending the concept of “neuromorphic” beyond using spiking neurons. This week we will briefly touch these topics – but first, a couple of EDA-related updates.
Cloud-based simulation of mechanical stress for TSMC’s 3D packaging
Ansys has collaborated with TSMC and Microsoft to validate a joint solution for analyzing mechanical stresses in multi-die 3D-IC systems manufactured with TSMC’s 3DFabric advanced packaging technologies. The solution is based on Ansys Mechanical finite element analysis software running on Microsoft Azure cloud infrastructure. 3D-IC systems often have large temperature gradients that lead to intense mechanical stresses between components due to differential thermal expansion. These stresses can lead to cracking or shearing of the connections between various elements. Simulating thermomechanical stress for large and complex devices, while maintaining predictive accuracy, requires substantial computing power.
New release of QuickLogic tool suite
QuickLogic has released version 2.4 of its Aurora eFPGA development tool suite. According to the company, this newest version integrates core tool enhancements that improve the eFPGA utilization and performance of designer’s RTL, particularly in the area of reconfigurable computing. The tool suite integrates fully open-source modules for scalability, longevity, and full code transparency. New features include asymmetric BlockRAM (BRAM) inferencing to reduce the need for manual modification of a user’s RTL design; single stage routing algorithm that boosts maximum operating frequency of a design by up to 24%; power calculation; and other new functionalities.
