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 EDACafe Editorial
Roberto Frazzoli
Roberto Frazzoli
Roberto Frazzoli is a contributing editor to EDACafe. His interests as a technology journalist focus on the semiconductor ecosystem in all its aspects. Roberto started covering electronics in 1987. His weekly contribution to EDACafe started in early 2019.

Shifting left HDL validation; security sign-off; a new eFPGA compiler; Rapidus-IBM packaging collaboration

June 11th, 2024 by Roberto Frazzoli

Let’s start with just a quick mention of a remarkable event in the IT world: at its recent Worldwide Developers Conference, Apple unveiled its long-awaited artificial intelligence strategy. Details of the AI innovations introduced by Apple – with a special focus on users’ privacy – can be found here. The Cupertino announcements, however, failed to impress the financial community, and Apple shares reportedly closed down nearly 2% after the event. Let’s now move to this week’s news roundup, which includes some pre-announcements concerning products that will be on display at the upcoming Design Automation Conference.

Sigasi’s shift-left approach to HDL validation

Sigasi has announced its new Visual HDL (SVH) product line, an integrated development environment that – according to the company – is able to take advantage of the shift-left methodology and give hardware designers and verification engineers better insight during the design progress. SVH enables them to manage HDL specifications by validating code early in the design flow, well before simulation and synthesis flows. SVH is fully integrated with Microsoft’s Visual Studio Code; lets users move through hierarchy views and graphics that update instantaneously as they make changes in their code; and flags problems while users enter HDL code. Starting with syntax and semantics, SVH enforces coding styles as recommended by safety standards such as DO-254 or ISO 26262 and catches UVM abuses. The new IDE comprises a tiered portfolio, offering a Designer Edition, a Professional Edition, an Enterprise Edition, and a Community Edition for non-commercial uses.

Real Intent’s tool for RTL security sign-off

Real Intent has announced Sentry, a hardware security static sign-off tool to protect designs against potential security vulnerabilities. The tool allows designers and security architects to incorporate hardware security sign-off early, as part of the RTL design process. According to the company, Sentry enables early hardware security sign-off at scale – supporting a hundred million gates with fast runtimes. Sentry analyzes data movement within the hardware, ensuring all paths adhere to stringent security protocols. In a single run, the tool performs path verifications simultaneously across multiple security specifications, such as data integrity (verifying that secure data transfers between protected domains without any corruption or unauthorized access), leakage prevention (ensuring sensitive data cannot reach unauthorized domains where it could be compromised) an interference safeguarding (stopping unauthorized data from reaching and interfering with secure domains).

Flex Logix’s efficient eFPGA compiler

Flex Logix has announced availability of eXpreso, its second generation EFLX eFPGA compiler. According to the company, eXpreso delivers up to 1.5x higher frequency, 2x denser LUT packing and 10x faster compile times for all existing EFLX tile and arrays. Result metrics unveiled by Flex Logix include an AES256 design that used to take six tiles compressed into just two, and a cryptography algorithm which achieved 98.6% LUT utilization.

Codasip’s low-power Risc-V core and new toolset

Codasip has introduced a new Risc-V low-power embedded processor core, and a new generation of its processor design automation toolset Codasip Studio. According to the company, the new Risc-V core L110 delivers up to 50% improvements in performance per watt and 20% smaller code size compared to similar cores in the market. It also offers extensive configurability and is fully customizable to achieve significant PPA improvements. The L110 targets small-area, low-power applications, such as state machine replacements, sensor controllers, and IoT edge. The new Codasip Studio Fusion offers a new level of customization, called Bounded Customization, enabling designers to extend the core with new instructions without risk because – according to the company – the functionality of the baseline core is guaranteed. A new verification framework substantially simplifies the verification of custom instructions.

Arm aims to capture 50% of Windows PC market

Arm is reportedly aiming to capture 50% of Windows PC market in five years. According to Arm’s CEO Rene Haas, Microsoft has prepped all the necessary developer tools to make sure that its software products can be ported to Arm and is “very, very much committed from a software standpoint.” However, there are uncertainties connected to a litigation between Arm and Qualcomm. Some observers reportedly expect the two companies to reach a settlement ahead of the trial.

“Chip war” updates

MetaX and Enflame, two Chinese chipmakers developing AI chips, reportedly submitted downgraded designs of their chips to TSMC in late 2023 to comply with U.S. restrictions. Those restrictions prevent TSMC from taking orders to produce highly sophisticated processors for Chinese chipmakers. Until recently, the production capacity of the most advanced Chinese foundry, SMIC, was entirely reserved for Huawei.

Rapidus and IBM expand collaboration to chiplet packaging technology

Expanding their preexisting partnership for 2-nanometer semiconductor technology, Japan’s Rapidus and IBM have announced a joint development partnership aimed at establishing mass production technologies for chiplet packages. As part of the agreement, IBM and Rapidus engineers will work in collaboration at IBM’s facilities in North America for R&D and manufacturing of semiconductor packaging for high-performance computer systems.

Further reading

The video recording of a recent interview offers additional details about Jensen Huang’s management style. Among many other things, Nvidia’s CEO said he has sixty people directly reporting to him, an unusually large leadership team. “Almost everything that I say, I say to everybody all at the same time,” he explained. “I really discourage one-on-ones,” he added, making it clear that the same also applies to discussing individual people’s issues. “I give you feedback right there in front of everybody,” he said. “Feedback is learning. For what reason are you the only person who should learn this? Now, you created the conditions because of some mistake that you made or silliness that you brought upon yourself. We should all learn from that opportunity.” Asked about the fact that he doesn’t like firing people, Huang said he thinks that people can improve. “I used to clean bathrooms, and now I’m the CEO of a company. I think you could learn it. (…) People know that I’d rather torture them into greatness,” he said.

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