Will artificial intelligence ever be able to replicate biological brains? It’s a fact that research is advancing on all fronts. On the one hand, the semiconductor industry continues to push transistor size reduction – examples can also be found in some of this year’s IEDM papers – paving the way to systems comprising an ever larger number of transistors. On the other hand, scientists have started bridging artificial intelligence and neurosciences to explore overall network structures – as in recent research from Cambridge University – extending the concept of “neuromorphic” beyond using spiking neurons. This week we will briefly touch these topics – but first, a couple of EDA-related updates.

Cloud-based simulation of mechanical stress for TSMC’s 3D packaging

Ansys has collaborated with TSMC and Microsoft to validate a joint solution for analyzing mechanical stresses in multi-die 3D-IC systems manufactured with TSMC’s 3DFabric advanced packaging technologies. The solution is based on Ansys Mechanical finite element analysis software running on Microsoft Azure cloud infrastructure. 3D-IC systems often have large temperature gradients that lead to intense mechanical stresses between components due to differential thermal expansion. These stresses can lead to cracking or shearing of the connections between various elements. Simulating thermomechanical stress for large and complex devices, while maintaining predictive accuracy, requires substantial computing power.

New release of QuickLogic tool suite

QuickLogic has released version 2.4 of its Aurora eFPGA development tool suite. According to the company, this newest version integrates core tool enhancements that improve the eFPGA utilization and performance of designer’s RTL, particularly in the area of reconfigurable computing.  The tool suite integrates fully open-source modules for scalability, longevity, and full code transparency. New features include asymmetric BlockRAM (BRAM) inferencing to reduce the need for manual modification of a user’s RTL design; single stage routing algorithm that boosts maximum operating frequency of a design by up to 24%; power calculation; and other new functionalities.

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According to the latest forecast from International Data Corporation (IDC), the semiconductor market has reached a bottom and will soon return to growth. For 2023, the market research firm has revised its September forecast and now estimates that worldwide semiconductor revenue this year will grow to $526.5 billion – down 12% from $598 billion in 2022, but up from the previously estimated $519 billion. For 2024, IDC expects year-over-year growth of 20.2% to $633 billion, up from $626 billion in the prior forecast. Growth in 2024-2026 will be fueled by AI silicon, which by the end of this forecast period will account for almost $200 billion in semiconductor revenues.

Synopsys.ai Copilot

Synopsys has announced Synopsys.ai Copilot, the result of a collaboration with Microsoft to integrate Azure OpenAI Service that brings GenAI into the design process for semiconductors. According to the company, Synopsys.ai Copilot works alongside designers in the Synopsys tools they use every day, enabling conversational intelligence, in natural language, across the design team. Deployable in any on-prem or on-cloud environment, Synopsys.ai Copilot integrates Microsoft Azure on-demand computing infrastructure.

Autodesk’s Fusion is now integrated with Cadence’s Allegro X and OrCAD X

Autodesk’s Fusion mechanical CAD platform has been integrated with Cadence’s Allegro X and OrCAD X PCB design platforms. The collaboration between the two companies aims at solving the problems of current manual design data methods, which require electrical and mechanical engineers to exchange files that can differ from design intent – resulting in errors, unnecessary re-work and costly delays. According to the two companies, the integrated solution enables seamless bi-directional communication between PCB designers and mechanical engineers.

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Japan’s government will reportedly allocate roughly $13 billion to boost its semiconductor industry. Part of this money is expected to be used to support TSMC and the recently founded Japanese foundry venture Rapidus. Let’s now move to the other news, which this week includes some announcements from Risc-V Summit North America.

Risc-V updates

Synopsys has extended its ARC Processor IP portfolio to include new Risc-V ARC-V Processor IP. The new Risc-V family includes the 32-bit ARC-V RMX embedded processor IP, scheduled to be available in Q2 of 2024; and the 32-bit ARC-V RHX real-time processor IP and 64-bit ARC-V RPX host processor IP, both scheduled to be available in the second half of 2024. Synopsys also announced it has joined the Risc-V International Board of Directors and Technical Steering Committee.

Ventana has announced the second generation of its Veyron family of datacenter Risc-V processors. According to the company, the new Veyron V2 is the highest performance Risc-V processor available today. It is offered in the form of chiplets and IP. Besides datacenters, V2 targets automotive, 5G, AI, and client applications.

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Risc-V starts attracting attention in the context of U.S.-China “chip war”: a bipartisan group of eighteen U.S. lawmakers that includes five Democrats is reportedly asking the Biden administration to prevent China from achieving dominance in Risc-V technology at the expense of U.S. national and economic security. Let’s now move to this week’s news roundup, starting with some EDA updates.

EDA updates: Cadence, Synopsys, Accellera

The new Cadence Voltus InsightAI is – according to the company – the industry’s first generative AI technology that automatically identifies the root cause of EM-IR drop violations early in the design process and selects and implements the most efficient fixes to improve power, performance, and area (PPA). As Cadence maintains, users of Voltus InsightAI can fix up to 95% of violations prior to signoff, leading to a 2X productivity improvement in EM-IR closure.

The new Synopsys Cloud OpenLink program enables chip designers to seamlessly access EDA tools and IP from multiple vendors in the Synopsys Cloud environment. As part of this initiative, the company is releasing an API specification that Synopsys Cloud OpenLink program members can use to deploy system-level integration with a secure and reliable transfer of entitlements to Synopsys Cloud.

Accellera has announced the availability of the Clock Domain Crossing (CDC) Draft Standard 0.1 for public review. This standard aims to ease SOC integration, which often involves combining in-house and externally purchased IPs. The public review is open through December 31, 2023.

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