Bridging the Frontier 
Paul Cohen
Paul Cohen is senior manager, ESD Alliance at SEMI. Now Open: Nominations for Phil Kaufman Award and Hall of FameMarch 5th, 2024 by Paul Cohen
Nominations are being accepted now through June 30 for the 2024 Phil Kaufman Award and the Phil Kaufman Hall of Fame, sponsored by the ESD Alliance, a SEMI Technology Community, and the IEEE Council on Electronic Design Automation (CEDA). Nomination forms are available for download on the SEMI website. The awards recognize individuals whose contributions made an impact within electronic system design in business, industry direction, promotion, technology and engineering, educational or mentoring. Established in 1994, the Phil Kaufman Award honors electronic design automation industry pioneer Phil Kaufman, who turned innovative technologies such as silicon compilation and emulation into businesses that have benefited electronic designers. Last year’s recipient was Dr. Lawrence T. Pileggi, Coraluppi Head and Tanoto Professor of Electrical and Computer Engineering at Carnegie Mellon University. The Phil Kaufman Hall of Fame posthumously recognizes individuals who made significant and noteworthy contributions through creativity, entrepreneurism and innovation to the electronic system design industry and were not recipients of the Phil Kaufman Award.
Reminder: Chiplet Security Panel Discussion Webinar March 14
A reminder: Registration is still open for the virtual “Chiplet Security—Current and Future” panel Thursday, March 14, from 9–10am PDT hosted by ESD Alliance and member company Silicon Assurance. Security threats are a growing concern because they can severely impact the electronic infrastructure and devices, especially the emerging chiplet-based design space where security measures must be used during the design flow to thwart security threats. The panel discussion addressing the seriousness of security threats will be moderated by Raj Gautam Dutta, CEO and co-founder of Silicon Assurance, a company focused on addressing trust and security assurance in the chip design flow. Panelists, who come from a broad cross-section of the chip design industry, will discuss the threats that can occur during the various stages of the design flow and at assembly and test. They will also consider the latest advancements and different approaches that can be employed to safeguard the future of chiplet-based design. The panel includes Swarup Bhunia, Semmoto Endowed Professor and Director of the Warren B. Nelms Institute; Steve Carlson, Director/Solutions Architect, Aerospace and Defense Solutions at Cadence Design Systems; John Hallman, Digital Verification Technology Solutions Manager for Siemens EDA; Serge Leef, Head of Secure Microelectronics at Microsoft; Salman Nasir, Senior Technical Program Manager from Battelle; and Ming Zhang, Vice President of R&D Acceleration at PDF Solutions. About The ESD Alliance The ESD Alliance, a SEMI Technology Community, represents members of the ecosystem that provide goods and services spanning the conceptualization, design, verification, manufacturing and deployment of semiconductor-based electronic systems. Our industry is essential to the global semiconductor industry as the driving force that enables new electronic systems to be conceived, designed and brought to market. The ESD Alliance focuses on initiatives and activities that bring value to our entire industry:
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