Note: The blog post below originally appeared on SEMI.

Protecting advanced computing infrastructure and the electronic devices that underpin our global economies, businesses and personal lives is essential in the face of growing cybersecurity threats. Cybersecurity protections have traditionally been focused on safeguarding software running on an existing electronic system that can be exploited by malware, trojans, or other malicious code. These threats can be hidden deep within an application, operating system, or BIOS.

However, we can no longer give short shrift to the possibility that security threats can infiltrate chip design. Malicious logic can lurk in the design, waiting to be triggered after the chip is manufactured and inside an electronic system. Recent headlines point to the vulnerability of hardware and how cyber threats now target the very building blocks of our digital infrastructure [1,2,3,4].

Hardware design threats can be introduced at various stages of the design flow including specification, architecture, RTL, gate, circuit, or layout. Addressing these threats during semiconductor design will require the industry to acknowledge the issues and re-think how designs are conceptualized and developed so that vulnerabilities can be mitigated as early as possible.
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Note: The Q&A below first appeared on SEMI in early February.

Aki Fujimura, CEO of D2S and a member of the ESD Alliance Governing Council, is an expert on curvilinear (aka curvy) chip design. He believes curvy chip design’s time has come and will ultimately replace the traditional Manhattan routing methods with their 90-degree-constrained turns. He recently discussed with me why curvy designs will lead to smaller, faster and more power efficient devices.

Smith: As the original creator of DEF/LEF as VP Engineering of Tangent in the late 1980s, you are very familiar with Manhattan routing methods. Tangent was first to commercialize area-based placement and routing with DEF, LEF, engineering change order (ECO), clock tree synthesis, scan insertion, timing-driven design in a then-solidifying synchronous design methodology. Tangent was acquired by Cadence in 1989 as a result. DEF/LEF are still the standard formats today for place and route. Isn’t the whole EDA infrastructure still pretty much making the Manhattan assumption?

Fujimura: A huge amount of innovation since then has improved considerably upon what we did back then. But you’re right that the basic approach to place and route is still making the Manhattan assumption with an alternating preferred direction (either horizontal or vertical) per layer. The Manhattan assumption was already there before Tangent came along. But prior to DEF/LEF, all interconnect was described as a path with (x,y) of each vertex. DEF/LEF halved the file sizes through the simple assumption that X or Y repeat because 99% of wires are alternatingly horizontal and vertical.

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