Posts Tagged ‘verification’
Tuesday, April 2nd, 2013
Cary Chin, Director of Technical Marketing at Synopsys, has an intriguing take on how to approach verification now that the mandate for design project managers is to meet the low power requirement of the target end-product. Chin says that if we look at verification in terms of fine and broad “granularity,” users will meet their verification goals with a lot less angst and anguish. However, at first glance, I had no idea what Chin was talking about…which is why we asked him to join us and talk about this idea.
Ed: Cary, you’ve been recently talking about granularity in verification, especially in terms of low power. What does this all mean?
Cary: When I think of granularity in low power design, I’m thinking about the size of the “chunks” that we manipulate to improve the energy efficiency (or “low power performance”) of a design. For example, in most of today’s low power methodologies, large functional blocks are the boundaries we work within – we can shut down these blocks or manipulate the voltage to save energy when peak performance isn’t required. This boundary level isn’t just a matter of convenience; our tools and methodologies for both implementation and verification can only deal with certain levels of complexity, so we are confined in many dimensions in how we can pursue finer granularity.
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Tags: EDA, Electronic Design Automation, granularity, hardware, low power, low-power verification, Moore's Law, power, RTL, semiconductors, software, Synopsys, UPF, verification
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Thursday, October 25th, 2012
 Piyush Sancheti In a recent article written by EDA industry watcher Ann Steffora Mutschler, Atrenta’s VP of Product Marketing Piyush Sancheti pointed to the curse of the verification double whammy for engineers:
“For verification engineers and for designers, this is a double whammy,” noted Piyush Sancheti, vice president of product marketing at Atrenta. “If you ask a digital design or digital verification team, they will tell you that low-power design and the introduction of analog/mixed-signal components on what used to be a simple digital chip is a significant verification challenge. For verification engineers what this means is your finite state machines or your control logic just got that much more complicated. If you go from 2 domains to 20 domains, your verification complexity just increased an order of magnitude.”
We caught up with Piyush in the Atrenta hallway and asked him to elaborate on his statement. Here’s what he said:
Ed: So what is the double whammy and why should we care?
Piyush: With the onset of A/MS and low power requirements, digital design teams now have to contend with two new foreign entries to their previous monolithic design environment.
Ed: And they are…?
Piyush: New logic blocks that are completely foreign to digital designers and the implementation of power management techniques like power & voltage domains. Voltage domains allow the timing critical portions of the design at a higher voltage (overdrive), and the rest at a lower voltage (underdrive). Power domains, on the other hand, allow one to turn off the power on entire blocks of the design when not in use.
Ed: Haven’t digital designers always needed to be conscious and conscientious about power?
Piyush: Not to the extent they must be these days. Here’s the challenge – say you are designing a chip for a smart phone. When you are watching a YouTube video, you don’t need the phone function, so you want to make sure that the phone functions are off. What’s the result? You’re saving power, or in consumer terms, preserving battery life. But, if the smart phone gets a call, you have to be sure the phone function turns on instantly, without adversely impacting your video viewing experience. So designers have to make sure the domains turn off and on in perfect harmony, almost like conducting a symphony.
So what’s the problem? New power management logic that designers are not used to has been thrust on them rapidly and recently. They need to get up to speed fast. This is not an easy job. Not only that, but you now have very complex finite state machines that switch these functions on and off seamlessly.
Ed: So what’s the solution?
Piyush: A comprehensive methodology for functional and structural verification.
Ed: Can you elaborate?
Piyush: These complex finite state machines must be verified exhaustively for functional correctness. You need to make sure that the various functions on your smart phone wake up and shut off in a timely manner without adversely impacting the device behavior, and ultimately the user experience. With structural verification you need to make sure that the perimeter of the voltage and power domains are properly secured. When you have signals crossing one voltage domain to another, you need voltage level shifters. Similarly, you need isolation logic between power domains, to ensure that signals don’t float to unknown values when a domain is powered off.
Ed: So what sort of tools and methodologies do you see out there to meet the double whammy challenge?
Piyush: Well, of course, I’m most familiar with the Atrenta platform. There are undoubtedly other ways to go about this job. But from what I see, SpyGlass Power is being used by many large chip and system companies for static signoff of power and voltage domains. SpyGlass Advanced Lint enables exhaustive finite state machine verification using formal techniques. And with our recent acquisition of NextOp Software, we now have BugScope to ensure dynamic verification (simulation) is covering all the corner cases that are now part of your design because of this increased complexity.
Ed: So your final words of wisdom?
Piyush: Verification of modern day SoC designs is a daunting task. But like any complex problem a systematic approach using a combination of static and dynamic verification techniques will help you reach your device ambitions faster.
– Note: Lee PR does work for Atrenta.
Tags: A/MS, analog mixed-signal, Atrenta, Chip Design, EDA, Electronic Design Automation, finite state machines, Low-Power High-Performance Engineering Community, NextOP, semiconductors, SoC, SpyGlass, verification
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Wednesday, October 10th, 2012
 Narayana Koduri’s article on Power Awareness in RTL Design Analysis was the second of two Atrenta articles that EE Times editor Brian Bailey named as the ten most-read contributed articles published in EDA Designline. Along with number one article Understanding Clock Domain Issues by Saurabh Verma and Ashima Dabare, Atrenta appears to be the only company with two articles in this top ten list.
So even though his article appeared in July 2012, we asked Narayana to give us an update on what he sees as the power awareness challenges. Here’s what he had to say.
Ed: Narayana, your article sure addressed a hot topic in SoC design. And judging by the readers you got, the design community liked what you had to say. What can you add to your July 2012 article?
Narayana: Thanks Ed. From what I can see, due to aggressive low power requirements, power domains are being implemented in a growing number of SoC designs to reduce both leakage and dynamic power.
Ed: How so?
Narayana: UPF or CPF can be used to define the power intent to capture information such as power domains, level shifter requirements, isolation cells, retention cells, power switch cells, etc. These specifications will help implementation tools and verification tools to deal with the power intent properly.
Ed: So how best to deal with power intent?
Narayana: RTL tools that verify aspects of the SoC such as clock domain crossings, testability, timing and routing congestion need to be aware of the power intent. If not, the verification is not complete and this may lead to design failures or a costly re-spin of the design. This need for power-aware verification is driving new requirements in the EDA tool flow.
NOTE: For an update on Understanding Clock Domain Issues see our blog of October 3.
Note: Lee PR does work for Atrenta
Tags: Atrenta, Brian Bailey, CDC, CPF, EDA, EDA DesignLine, EE Times, low power, Power awareness, power domains, register transfer level, RTL, semiconductors, SoC, UPF, verification
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Monday, July 30th, 2012
 Mike Gianfagna, VP of Corporate Marketing
With Atrenta’s acquisition of NextOp concluded and the corporate and technology integration going forward, we checked in with Atrenta’s Mike Gianfagna about what this means for the industry. Dawn of a new business day for EDA?
Ed: It’s been about a month now since Atrenta bought NextOp. What has to happen now?
Mike: The fanfare is waning. The news has been reported and analyzed. The two company’s web sites are one. And now the real work begins as we integrate NextOp technology with Atrenta technology.
Ed: So what does all this mean?
Mike: For Atrenta, it means accelerated growth in the SoC Realization market. We can now address design and verification challenges at RTL and above. For our customers, this will mean improved schedule predictability and lower cost.
Ed: So now you add functional verification to the RTL platform for SoC design, right?
Mike: Actually, NextOp’s technology goes beyond functional verification of SoCs. It also helps with IP qualification and IP reuse – very important focus areas for Atrenta. This technology will improve the completeness and effectiveness of our IP Kit.
Customers will get the previous benefits of early analysis coupled with functional verification – an area that continues to be very time consuming, expensive and somewhat unpredictable.
Ed: So what does this mean to the EDA industry?
Mike: I hope it has a positive impact on the industry as well. EDA has been stagnant for too long. The same customers buying the same tools from the same vendors. It’s time to shake things up a bit. It’s time for new methodologies, new approaches, new business models and more positive exits for all those hard-working people at private EDA companies. Can Atrenta’s acquisition of NextOp contribute to this trend in some meaningful way? I certainly hope so.
NOTE: Lee PR does work for Atrenta.
Tags: acquisitions, Atrenta, EDA, Electronic Design Automation, Finance, functional verification, IP, IP qualification, IP reuse, NextOP, register transfer level, RTL, semiconductors, SoC, SoC Realization, System on Chip, verification
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Wednesday, June 20th, 2012
Gary Smith’s statement about the Atrenta acquisition of NextOp has been bandied about this morning in the news….“This could be the start of something big, and NextOp was an excellent place to start.”
See today’s news and analysis about Atrenta’s acquisition of assertion synthesis vendor NextOp plus an interview with Atrenta and NextOp execs in the following online publications:
EDA Café Blog: What Would Joe Do?
EDA Express
EE Daily News
EE Times News & Analysis
EE Times: EDA DesignLine
Gabe on EDA
SemiWiki
System-Level Design
Tech Design Forums
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Lee PR does work for Atrenta
Tags: Assertion Synthesis, Atrenta, EDA, EDA Cafe, EDA DesignLine, EDA Tech Design Forums, EE Daily News, EE Times, Electronic Design Automation, Gabe on EDA, Gary Smith, Jim Hogan, M&A, NextOP, NextOp Software, register transfer level, RTL, Semiconductor IP, semiconductors, SemiWiki, software, System-Level Design, verification
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Wednesday, June 20th, 2012
Atrenta Accelerates Growth in Front End Design with Acquisition of NextOp Software, Inc.
SpyGlass design productivity enhancements expanded to functional verification for semiconductor and consumer electronics developers
SAN JOSE, Calif — June 20, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced that it has acquired NextOp Software, Inc., a leading provider of assertion synthesis technology. Atrenta’s products focus on improving efficiency and reducing cost for the design of complex semiconductor IP and system-on-chip (SoC) devices while NextOp’s products focus on improving efficiency and reducing cost for the functional verification of IPs and SoCs. The combination of both company’s products creates a more complete SoC Realization platform.
The acquisition of NextOp allows Atrenta to expand its de-facto standard SpyGlass® register transfer level (RTL) platform to include functional verification — an important and costly component of advanced SoC design. Utilizing patented static and formal analysis techniques, the SpyGlass platform currently provides RTL design efficiency improvements in the areas of linting, clock synchronization, power optimization, testability, timing constraints and physical routing congestion. The SpyGlass platform will now be expanded to include functional verification support using NextOp’s patented dynamic assertion synthesis technology, resulting in verification efficiency improvements for semiconductor and consumer electronics developers.
“The addition of NextOp’s functional verification technology will give our customers a distinct advantage by providing complete coverage of front end design activities,” said Dr. Ajoy Bose, chairman, president and CEO of Atrenta. “Atrenta’s customers have come to rely on SpyGlass to verify a broad range of design intent, but functional verification was a missing part of our platform. NextOp’s assertion synthesis completes this part of our offering – Atrenta customers will now have added confidence that their designs will work as expected while meeting schedule and performance requirements. We are very excited to bring these innovative solutions and the resulting expanded benefits to our large customer base. ”
“Atrenta is one of the largest private EDA companies,” said Dr. Yunshan Zhu, president and CEO of NextOp Software. “NextOp has pioneered assertion synthesis technology. Our tool is now widely deployed in production at multiple tier 1 customers – many of whom also use SpyGlass. Atrenta’s world-class field operation will further accelerate the mainstream adoption of assertion synthesis.”
“I’ve heard good things about NextOp’s verification technology from some impressive customers – the combination of Atrenta’s RTL design and NextOp’s RTL verification technology will improve the entire SoC Realization process,” said Jim Hogan, EDA industry veteran and private investor. “I’m also glad to see private/private acquisitions like this happening again after such a long dry spell. Atrenta could be leading a trend in renewed growth for the EDA sector.”
“With the acquisition of Magma there has been renewed talk about a roll-up in the middle of the EDA community,” saidGary Smith, founder and chief analyst for Gary SmithEDA. “The most obvious candidates are the RTL sign-off tool vendors, and the most talked about driver, of the roll-up, has been Atrenta. This could be the start of something big, and NextOp was an excellent place to start.”
NextOp’s BugScope assertion synthesis tool will be sold and supported by the combined Atrenta/NextOp worldwide field organization. Dr. Yunshan Zhu will assume the role of vice president, new technologies reporting to Dr. Ajoy Bose. Dr. Yuan Lu, co-founder and CTO of NextOp will assume the role of chief verification architect reporting to Dr. Zhu. Financial terms of the transaction were not disclosed.
About Assertion Synthesis
Assertion synthesis leverages design and test bench information to automatically generate high quality assertions and functional coverage properties. Generating assertions and coverage properties manually is tedious and error-prone. Assertions represent a machine-readable version of design intent and are used to improve verification completeness. Functional coverage properties identify functional coverage deficiencies providing guidance for verification teams. When used together, design teams can reduce functional verification time and improve overall functional coverage, resulting in lower design costs, better first-time silicon success and improved quality.
About Atrenta
Atrenta’s SpyGlass® Predictive Analysis software platform significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs. SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com
About NextOp Software
NextOp Software, Inc. is focused on delivering assertion-based verification solutions that allow design and verification teams to uncover bugs, expose functional coverage holes, and increase verification observability. NextOp’s BugScope assertion synthesis is the first product to automatically generate whitebox assertions and functional coverage properties in SVA, PSL and Verilog formats. BugScope’s properties are used to drive progressive, targeted verification via robust, executable design specifications for existing simulation, formal and emulation flows. The company is headquartered at2900 Gordon Avenue, Suite 100,Santa Clara,CA95051. For more information, visit www.nextopsoftware.com or call +1 408-830-9885.
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© 2012 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo and SpyGlass are registered trademarks of Atrenta Inc. BugScope and NextOp are trademarks of NextOp Software, Inc. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.
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Lee PR does work for Atrenta
Tags: Ajoy Bose, Assertion Synthesis, Atrenta, EDA, Electronic Design Automation, Gary Smith, Jim Hogan, NextOP, NextOp Software, register transfer level, RTL, semiconductors, SoC, software, SypGlass, System on Chip, verification, Yunshan Zhu
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Monday, January 18th, 2010
2009 was a rough year for an already stagnant EDA world. Looking to 2010, Liz Massingill and I asked industry colleagues, opinion makers and friends what each of them saw as the BIG trend for 2010.
Here’s what they said.
Karen Bartleson, Blogger, The Standards Game, Synopsys
http://synopsysoc.org/thestandardsgame/
The big trend in EDA for 2010 will be the acceptance of social media as an additional means for communicating with customers, partners, and competitors.
Now that blogging is settling in as a viable source of information from media people, company experts, and independent publishers, more new media tools will come into play. Not all tools are right for everyone or every situation, so the EDA industry will explore the options and experiment with a variety of community-development activities.
LinkedIn and Facebook will offer special interest groups a place to congregate. Twitter will be tested by more people – who today are curious or skeptical – as a means of immediate, brief interaction. EDA suppliers will offer new communication channels and those that are truly value-add will thrive.
The EDA world won’t change overnight, but the trends in social media will be noticeable.
Graham Bell, Director of Sales and Marketing, EDACafe
http://www10.edacafe.com/blogs/grahambell/
The BIG trend will be that designers need ALL of the technology that EDA companies have been working on and introduced in the last 18 months.
There is a lot of design work being done at 45nm and all the established tools are running at the edge of their capabilities.
New generations of parasitic extraction, static and statistical timing analysis, and automated property verification are just some of the important technologies that will be needed by design teams.
Mike Gianfagna, Vice President, Marketing, Atrenta, Inc.
http://www.atrenta.com
In 2010, we’ll see an accelerated move to doing more design at higher levels of abstraction.
Chip complexity and the skyrocketing cost of physical design, along with the advent of 3D stacks is forcing this. Designers just won’t be able to iterate in the back end in 2010 and beyond. It’ll take too long and cost too much.
Power management, design verification, design for test and timing closure will all be “close to done” before handoff to synthesis and place & route. The traditional backend flow of IC design will become a more predictable, routine process, which will accelerate its trend toward commoditization and consolidation.
This move to higher levels of abstraction will also have implications for IP selection and chip assembly. This will compel a new genre of tools to emerge. Standards like IP-XACT will help this process to take hold. Perhaps this is what ESL will become.
Richard Goering, longtime EDA editor and currently manager of the Cadence Industry Insights blog
http://www.cadence.com/Community/blogs/ii
I think the Big EDA Trend for 2010 will be SoC integration.
There will be a renewed focus on the challenges of integrating existing IP, providing breakthrough technology for design teams to quickly and reliably
assemble complex SoCs from integration-ready IP blocks, and then run
full-chip verification including both analog and digital components.
ESL is part of this story because there’s a need to move to
transaction-level IP creation, verification and integration. Hardware/ software integration and verification and will also become part of
the drive towards SoC integration.
Harry Gries, the ASIC Guy, EDA blogger
http://theasicguy.com/
As for the EDA trend in 2010, I think that EDA companies, when they recover, will choose not to hire more sales and marketing people but will invest more in other marketing tools on the Web or using social networking strategies.
A good example is a company like Xuropa, which is actually a client of mine, under full disclosure. They help EDA companies put their tools on the Web in order to help them reduce their costs for demos, product evaluations, etc.
I think that will see a lot of interest in the upcoming year as companies look for ways to do “more with less”. User group events may also move online, just like this year’s CDNLive was a virtual event rather than a real live event. Xilinx and Avnet sponsored an X-Fest this year that was also an online event. Things are moving online fast and economics will drive that.
Grant Martin, EDA blogger
http://www.chipdesignmag.com/martins/
In 2010, we’ll see the steady progress towards usable ESL tool and methodology adoption by design groups.
The areas of greatest real ESL use are the high level synthesis of data crunching blocks used in various DSP-type applications (signal and media processing), the increasing adoption of processor/SW-centric design methods, and the increased creation and use of virtual prototype models.
(Brian Bailey and I have a new book from Springer coming out in the new year on practical ESL use methods: “ESL Models and their Application: Electronic System Level Design and Verification in Practice”. See for a summary. )
Dan Nenni, EDA blogger
http://danielnenni.com/
For EDA, 2010 will be the year of the foundry. Foundries will drive new EDA flows and business models.
The TSMC Open Initiative Platform
is but the tip of the iceberg. If EDA and IP companies do NOT join forces with the foundries and take arms against the sea of semiconductor troubles – they will continue to suffer the slings and arrows of outrageous economic misfortune.
Coby Zelnik, CEO, Sagantec North America, Inc.
http://www.sagantec.com
In 2010, we will see more designs taping out in 40nm.
In an effort to minimize risk, cost and time to market, design reuse will be
maximized; many of them will be migrations of existing 90nm and 65nm products or derivative products with minor updates and tweaks.
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Tags: 3D, architectural, Coby Zelnik, Dan Nenni, EDA trends, ESL, Graham Bell, Grant Martin, Harry the ASIC Guy, high level synthesis, IP-XACT, Karen Bartleson, Mike Gianfaga, power, Richard Goering, RTL, social media, verification
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