Posts Tagged ‘NextOP’
Thursday, October 25th, 2012
 Piyush Sancheti In a recent article written by EDA industry watcher Ann Steffora Mutschler, Atrenta’s VP of Product Marketing Piyush Sancheti pointed to the curse of the verification double whammy for engineers:
“For verification engineers and for designers, this is a double whammy,” noted Piyush Sancheti, vice president of product marketing at Atrenta. “If you ask a digital design or digital verification team, they will tell you that low-power design and the introduction of analog/mixed-signal components on what used to be a simple digital chip is a significant verification challenge. For verification engineers what this means is your finite state machines or your control logic just got that much more complicated. If you go from 2 domains to 20 domains, your verification complexity just increased an order of magnitude.”
We caught up with Piyush in the Atrenta hallway and asked him to elaborate on his statement. Here’s what he said:
Ed: So what is the double whammy and why should we care?
Piyush: With the onset of A/MS and low power requirements, digital design teams now have to contend with two new foreign entries to their previous monolithic design environment.
Ed: And they are…?
Piyush: New logic blocks that are completely foreign to digital designers and the implementation of power management techniques like power & voltage domains. Voltage domains allow the timing critical portions of the design at a higher voltage (overdrive), and the rest at a lower voltage (underdrive). Power domains, on the other hand, allow one to turn off the power on entire blocks of the design when not in use.
Ed: Haven’t digital designers always needed to be conscious and conscientious about power?
Piyush: Not to the extent they must be these days. Here’s the challenge – say you are designing a chip for a smart phone. When you are watching a YouTube video, you don’t need the phone function, so you want to make sure that the phone functions are off. What’s the result? You’re saving power, or in consumer terms, preserving battery life. But, if the smart phone gets a call, you have to be sure the phone function turns on instantly, without adversely impacting your video viewing experience. So designers have to make sure the domains turn off and on in perfect harmony, almost like conducting a symphony.
So what’s the problem? New power management logic that designers are not used to has been thrust on them rapidly and recently. They need to get up to speed fast. This is not an easy job. Not only that, but you now have very complex finite state machines that switch these functions on and off seamlessly.
Ed: So what’s the solution?
Piyush: A comprehensive methodology for functional and structural verification.
Ed: Can you elaborate?
Piyush: These complex finite state machines must be verified exhaustively for functional correctness. You need to make sure that the various functions on your smart phone wake up and shut off in a timely manner without adversely impacting the device behavior, and ultimately the user experience. With structural verification you need to make sure that the perimeter of the voltage and power domains are properly secured. When you have signals crossing one voltage domain to another, you need voltage level shifters. Similarly, you need isolation logic between power domains, to ensure that signals don’t float to unknown values when a domain is powered off.
Ed: So what sort of tools and methodologies do you see out there to meet the double whammy challenge?
Piyush: Well, of course, I’m most familiar with the Atrenta platform. There are undoubtedly other ways to go about this job. But from what I see, SpyGlass Power is being used by many large chip and system companies for static signoff of power and voltage domains. SpyGlass Advanced Lint enables exhaustive finite state machine verification using formal techniques. And with our recent acquisition of NextOp Software, we now have BugScope to ensure dynamic verification (simulation) is covering all the corner cases that are now part of your design because of this increased complexity.
Ed: So your final words of wisdom?
Piyush: Verification of modern day SoC designs is a daunting task. But like any complex problem a systematic approach using a combination of static and dynamic verification techniques will help you reach your device ambitions faster.
– Note: Lee PR does work for Atrenta.
Tags: A/MS, analog mixed-signal, Atrenta, Chip Design, EDA, Electronic Design Automation, finite state machines, Low-Power High-Performance Engineering Community, NextOP, semiconductors, SoC, SpyGlass, verification
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Tuesday, August 7th, 2012
 Yesterday we heard from Jim Hogan on the NextOp acquisition. Today Gary Smith chimes in on NextOp and the recent Springsoft buyout.
Ed: What do the Atrenta acquisition of NextOp and the Synopsys acquisition of Springsoft mean to EDA?
Gary: Technology wise the Atrenta acquisition means that the Silicon Virtual Prototype is becoming a reality. Business wise it could be the start of the roll-up in the middle.
Springsoft was always a possible roller-upper but generally thought of as a long shot because of theirTaiwanheadquarters. Springsoft certainly makes Synopsys stronger, especially with the Laker analog product, but doesn’t affect the SVP or the RTL sign-off tool market. Debug is just being rolled up into the simulator.
Ed: What sort of new day does it herald for EDA?
Gary: With the creation of the SVP we now have the RTL sign-off established. This then is the breakpoint between design and implementation, just as the gate-level netlist was in the past. This will free up a large group of designers, and enable a new larger group of designers, which in-turn will cause the explosion of new systems development.
Ed: What’s the significance?
Gary: Growth, opportunity, money; the usual stuff.
Lee PR does work for Atrenta
Tags: acquisitions, Atrenta, buyouts, Chip Design, EDA, Electronics Design Automation, Finance, Gary Smith, NextOP, RTL, Semiconductor IP, semiconductors, Silicon Virtual Prototype, Springsoft, SVP, Synopsys
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Monday, August 6th, 2012
We’ve seen several acquisitions in the past month or so…and wanted to get a sense of what these purchases might or might not indicate about where EDA is going. So we went to the premier visionary and investor to get his take on how the EDA world will be affected by this apparent consolidation.
Ed: What do these acquisitions over the past month or so mean to EDA?
Jim: I like the Atrenta NextOp acquisition for several of points of view. In my world mergers are successful in EDA if:
1. there is no product overlap
2. the sales channel can immediately sell the product. Usually this means that the AEs support it or at least will be product within 30 days of purchase.
There is a ton of synergy with the Atrenta sales channel. This is important to ensure the ROI is met, typically a two to three year process.
3. customers support the merger. In other words, they see that the product is going to be continued to be supported with R&D and AEs.
4. the team remains at least two years to ensure intellectual property transition. In the case of Atrenta and NextOp, I believe all conditions are being met. Thus I expect a successful integration of NextOp and ROI.
In addition it speaks to Atrenta’s forward progress to being an IPO candidate. One issue for EDA is that companies exiting over the last ten years have been through acquisition. If we can see an IPO of a well-run and well-performing company, it attracts the attention of shareholders but also ensures an exit other than acquisition for other EDA companies. This will attract investors and thus we’ll see startups funded. This is a win-win for the entire ecosphere including customers.
I believe one of the key ingredients in an EDA company going public besides top line revenue of greater than $50m with 25% CAGR and margin of $10m or greater is the ability of the management team to acquire and integrate complementary startups. With Atrenta acquiring NextOp, I believe they are on their way.
Good luck to them because their IPO will be good for EDA by bringing excitement and notice to the sector.
Lee PR does work for Atrenta
Tags: Atrenta, EDA, Electronic Design Automation, Finance, functional verification, Jim Hogan, mergers, NextOP, Semiconductor IP, semiconductors
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Monday, July 30th, 2012
 Mike Gianfagna, VP of Corporate Marketing
With Atrenta’s acquisition of NextOp concluded and the corporate and technology integration going forward, we checked in with Atrenta’s Mike Gianfagna about what this means for the industry. Dawn of a new business day for EDA?
Ed: It’s been about a month now since Atrenta bought NextOp. What has to happen now?
Mike: The fanfare is waning. The news has been reported and analyzed. The two company’s web sites are one. And now the real work begins as we integrate NextOp technology with Atrenta technology.
Ed: So what does all this mean?
Mike: For Atrenta, it means accelerated growth in the SoC Realization market. We can now address design and verification challenges at RTL and above. For our customers, this will mean improved schedule predictability and lower cost.
Ed: So now you add functional verification to the RTL platform for SoC design, right?
Mike: Actually, NextOp’s technology goes beyond functional verification of SoCs. It also helps with IP qualification and IP reuse – very important focus areas for Atrenta. This technology will improve the completeness and effectiveness of our IP Kit.
Customers will get the previous benefits of early analysis coupled with functional verification – an area that continues to be very time consuming, expensive and somewhat unpredictable.
Ed: So what does this mean to the EDA industry?
Mike: I hope it has a positive impact on the industry as well. EDA has been stagnant for too long. The same customers buying the same tools from the same vendors. It’s time to shake things up a bit. It’s time for new methodologies, new approaches, new business models and more positive exits for all those hard-working people at private EDA companies. Can Atrenta’s acquisition of NextOp contribute to this trend in some meaningful way? I certainly hope so.
NOTE: Lee PR does work for Atrenta.
Tags: acquisitions, Atrenta, EDA, Electronic Design Automation, Finance, functional verification, IP, IP qualification, IP reuse, NextOP, register transfer level, RTL, semiconductors, SoC, SoC Realization, System on Chip, verification
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Wednesday, June 20th, 2012
Gary Smith’s statement about the Atrenta acquisition of NextOp has been bandied about this morning in the news….“This could be the start of something big, and NextOp was an excellent place to start.”
See today’s news and analysis about Atrenta’s acquisition of assertion synthesis vendor NextOp plus an interview with Atrenta and NextOp execs in the following online publications:
EDA Café Blog: What Would Joe Do?
EDA Express
EE Daily News
EE Times News & Analysis
EE Times: EDA DesignLine
Gabe on EDA
SemiWiki
System-Level Design
Tech Design Forums
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Lee PR does work for Atrenta
Tags: Assertion Synthesis, Atrenta, EDA, EDA Cafe, EDA DesignLine, EDA Tech Design Forums, EE Daily News, EE Times, Electronic Design Automation, Gabe on EDA, Gary Smith, Jim Hogan, M&A, NextOP, NextOp Software, register transfer level, RTL, Semiconductor IP, semiconductors, SemiWiki, software, System-Level Design, verification
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Wednesday, June 20th, 2012
Atrenta Accelerates Growth in Front End Design with Acquisition of NextOp Software, Inc.
SpyGlass design productivity enhancements expanded to functional verification for semiconductor and consumer electronics developers
SAN JOSE, Calif — June 20, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced that it has acquired NextOp Software, Inc., a leading provider of assertion synthesis technology. Atrenta’s products focus on improving efficiency and reducing cost for the design of complex semiconductor IP and system-on-chip (SoC) devices while NextOp’s products focus on improving efficiency and reducing cost for the functional verification of IPs and SoCs. The combination of both company’s products creates a more complete SoC Realization platform.
The acquisition of NextOp allows Atrenta to expand its de-facto standard SpyGlass® register transfer level (RTL) platform to include functional verification — an important and costly component of advanced SoC design. Utilizing patented static and formal analysis techniques, the SpyGlass platform currently provides RTL design efficiency improvements in the areas of linting, clock synchronization, power optimization, testability, timing constraints and physical routing congestion. The SpyGlass platform will now be expanded to include functional verification support using NextOp’s patented dynamic assertion synthesis technology, resulting in verification efficiency improvements for semiconductor and consumer electronics developers.
“The addition of NextOp’s functional verification technology will give our customers a distinct advantage by providing complete coverage of front end design activities,” said Dr. Ajoy Bose, chairman, president and CEO of Atrenta. “Atrenta’s customers have come to rely on SpyGlass to verify a broad range of design intent, but functional verification was a missing part of our platform. NextOp’s assertion synthesis completes this part of our offering – Atrenta customers will now have added confidence that their designs will work as expected while meeting schedule and performance requirements. We are very excited to bring these innovative solutions and the resulting expanded benefits to our large customer base. ”
“Atrenta is one of the largest private EDA companies,” said Dr. Yunshan Zhu, president and CEO of NextOp Software. “NextOp has pioneered assertion synthesis technology. Our tool is now widely deployed in production at multiple tier 1 customers – many of whom also use SpyGlass. Atrenta’s world-class field operation will further accelerate the mainstream adoption of assertion synthesis.”
“I’ve heard good things about NextOp’s verification technology from some impressive customers – the combination of Atrenta’s RTL design and NextOp’s RTL verification technology will improve the entire SoC Realization process,” said Jim Hogan, EDA industry veteran and private investor. “I’m also glad to see private/private acquisitions like this happening again after such a long dry spell. Atrenta could be leading a trend in renewed growth for the EDA sector.”
“With the acquisition of Magma there has been renewed talk about a roll-up in the middle of the EDA community,” saidGary Smith, founder and chief analyst for Gary SmithEDA. “The most obvious candidates are the RTL sign-off tool vendors, and the most talked about driver, of the roll-up, has been Atrenta. This could be the start of something big, and NextOp was an excellent place to start.”
NextOp’s BugScope assertion synthesis tool will be sold and supported by the combined Atrenta/NextOp worldwide field organization. Dr. Yunshan Zhu will assume the role of vice president, new technologies reporting to Dr. Ajoy Bose. Dr. Yuan Lu, co-founder and CTO of NextOp will assume the role of chief verification architect reporting to Dr. Zhu. Financial terms of the transaction were not disclosed.
About Assertion Synthesis
Assertion synthesis leverages design and test bench information to automatically generate high quality assertions and functional coverage properties. Generating assertions and coverage properties manually is tedious and error-prone. Assertions represent a machine-readable version of design intent and are used to improve verification completeness. Functional coverage properties identify functional coverage deficiencies providing guidance for verification teams. When used together, design teams can reduce functional verification time and improve overall functional coverage, resulting in lower design costs, better first-time silicon success and improved quality.
About Atrenta
Atrenta’s SpyGlass® Predictive Analysis software platform significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs. SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com
About NextOp Software
NextOp Software, Inc. is focused on delivering assertion-based verification solutions that allow design and verification teams to uncover bugs, expose functional coverage holes, and increase verification observability. NextOp’s BugScope assertion synthesis is the first product to automatically generate whitebox assertions and functional coverage properties in SVA, PSL and Verilog formats. BugScope’s properties are used to drive progressive, targeted verification via robust, executable design specifications for existing simulation, formal and emulation flows. The company is headquartered at2900 Gordon Avenue, Suite 100,Santa Clara,CA95051. For more information, visit www.nextopsoftware.com or call +1 408-830-9885.
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© 2012 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo and SpyGlass are registered trademarks of Atrenta Inc. BugScope and NextOp are trademarks of NextOp Software, Inc. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.
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Lee PR does work for Atrenta
Tags: Ajoy Bose, Assertion Synthesis, Atrenta, EDA, Electronic Design Automation, Gary Smith, Jim Hogan, NextOP, NextOp Software, register transfer level, RTL, semiconductors, SoC, software, SypGlass, System on Chip, verification, Yunshan Zhu
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