In the following video, Warren Savage, CEO of IPextreme, talks with Mike Gianfagna, VP of Corporate Marketing at Atrenta, about collaboration – with TSMC and the Constellations partners.
Mike’s dream is for “a vibrant industry with a well-defined quality metric.”
With less than 3 weeks away until DAC’13, Liz and I asked Warren Savage about IPextreme’s and Constellations’ planned presence there. Warren is not only founder and CEO of IPextreme, but also head of the IP consortium, Constellations.
We caught up with Warren recently, and Mike Gianfagna, VP of Corporate Marketing at Atrenta (Atrenta is a Constellations partner), happened to be there. So, the two of them let us in on what Constellations would be up to at DAC.
Liz: Warren, what play does IP have at DAC this year?
Warren Savage President and CEO IPextreme
Warren: Change is slow, but IPextreme and Constellations are happy to report change is afoot and our workshop at DAC serves as a prime example of this. Together with TSMC and our Constellations partners Atrenta and Sonics, we are pleased to present “Driving Quality to the Desktop of the DAC Engineer” on Sunday, June 2 from 1:00 to 5:00 PM. This workshop showcases a foundry, two IP companies, and an EDA company working together—exactly as we do every day.
Why, then, is this the first DAC workshop of its kind? Why have the ties binding us together in the semiconductor ecosystem not been highlighted before? Perhaps the old saying, “If all you have is a hammer, everything looks like a nail,” is the only explanation. At the end of the day, our customers need all of us – both IP providers and EDA vendors. We owe it to them not only to recognize that, but also to make their lives easier by working together.
The final word on the BIG theme(s) for DAC comes from Brian Bailey, Editor of EE Times EDA Designline……
For many people, the attendance numbers seem to be the number one issue on their minds this year. DAC has never been to Austin in its 50 year history and only once been to Texas. Yet there is, and has always been, a very large design community in that area, a group of people that have perhaps been overlooked. A head count seems to be a very unimportant number, even though it is an easy metric. But we are an intelligent industry that should know a lot about metrics and I think there are more useful metrics in this case, such as the number of first time attendees.
These two trend setters share their opinions on the BIG DACthemes in 2013.
I see two related trends:
1) More signoff activity earlier in the design flow
2) More focus on IP quality and usability
Both of these trends represent a maturing of design tools and business models. Because of the tremendous complexity that sub-20 nm design brings, it becomes more important to get the design right as early as possible. The tools are maturing in the earlier stages, and more designers are demanding clean reports, or sign-off level quality audits as a result. This is helping to reduce schedule delays and design costs – good for the industry.
Semiconductor IP is also maturing – both use models and business models. There is a growing focus on reporting delivered quality and robustness. This will allow IP providers that deliver the best IP to flourish. Also good for the industry. We’ll see an increase in conversations about IP providers collaborating with the rest of the ecosystem at DAC. Another good trend.
DAC is upon us….and in Austin, of all places – the island in the middle of Texas.
As it’s getting closer, we were wondering what the BIG theme is for the 50th DAC. So, we asked a few of our friends and colleagues in the industry. Here’s what a few of them had to say.
I expect DAC to continue to explore low power challenges, with much talk about solving FinFET issues at 14 and 10 nm. Then there is the ever expanding SoC and how to handle all of the challenges that come with greater integration and IP reuse. Finally, what’s DAC without a discussion of Moore’s Law and whether it will/won’t continue to define industry progress in the years to come?
Atrenta has pulled together quite a slate of customers, partners, an industry observer and EDA’s premier investor to talk about the value SpyGlass brings to each of their realms. It’ll be interesting to hear how this signature product has proliferated in different environments! Atrenta invites you to stop by and hear how SpyGlass improves productivity @ Xilinx, Vivante, Sonics and Arteris and why Dan Nenni and Jim Hogan see SpyGlass as the consummate ubiquitous product in EDA.
Founded in 2005 by Steve Yang and Jason Xing, the company’s been busy over the last year. How? Merging with analog EDA vendor Huada Empyrean Software (HES), getting that US$28M infusion to fund global R&D, customer support and sales expansion, and working on OpenAccess-based product lines that we’ll probably see in some integrated form toward the end of 2012.
ICScape’s booth will greet attendees right at the entrance to the exhibit floor, in Booth 1602. The company’s executives will be there to:
1) talk about its technology,
2) introduce current customers (a major silicon valley Fabless IC company and a major Silicon Valley analog device company) who will also be available at the booth to share firsthand experience,…..and
Maybe Atrenta is saying goodbye to the thought-bubble guy…..
Atrenta’s SpyGlass has always been the dominant name in the company’s brand portfolio,and for good reason. It’s the dominant product in RTL design analysis, verification and optimization.
Now, Atrenta is reconfiguring its product lineup to formalize this state of affairs. SpyGlass now becomes the unifying platform for all Atrenta products. Sort of the mother ship that all Atrenta products are based on.
So what’s a unified platform? All the tools now share a common set up and debugging methodology and tighter GUI. And what can users verify and optimize from this new unified platform? Syntax, power, testability, clock synchronization, timing and routing congestion. All at the RTL stage, well before detailed implementation begins.
