Doulos has partnered with Aldec to deliver this Friday’s webinar, ‘Easier UVM: Helping FPGA Designers Get Started with UVM’ . Presented by Doulos CTO, John Aynsley, the 1 hour webinar includes live Q&A so it’s a great opportunity to find out how Easier UVM can work for you. The webinar includes examples from the Easier UVM Code Generator running under Aldec Riviera-PRO™.
Aldec Design and Verification
Posts Tagged ‘uvm’
Helping FPGA Designers get started with UVM
Tuesday, September 8th, 2015How HES™ Technology Solved Problems for These Users
Monday, October 20th, 2014
Recognizing a problem that engineers are facing and developing a solution has been Aldec’s rather straight-forward mantra for going on thirty years now. Aldec launched its Hardware Emulation Solutions (HES) product in 2003, integrating RTL simulation with hardware emulation, and offering hardware and software design teams the ability to work concurrently. Today HES™ is a fully automated and scriptable HybridVerification and Validation environment for SoC and ASIC designs capable of bit-level simulation acceleration, SCE-MI 2.1 transaction emulation, hardware prototyping, and virtual modeling.
The 80s music at DAC was my idea. You’re welcome.
Tuesday, June 24th, 2014
If you attended the Monday Night Reception at DAC 2014, you were greeted with a blast of 80s pop music. If you then said to yourself, “I’d like to meet the genius behind that idea” – that would be me. A few weeks before DAC, our marketing manager came to me with the task of being the DJ for the Monday night reception. As soon as I heard “DJ” I envisioned turntables, cool headphones, disco lights and all the fame that follows. My dreams were dashed a few moments later when she explained that I would only have a PA and a laptop.
Undaunted, I resolved to be the best DJ in the history of DAC Monday Night Networking Receptions. The first challenge was finding music everyone would enjoy. I naturally settled on 80s pop as my genre. I had the brilliant idea of picking a few songs from each year and playing it as a progressive 80s timeline during the evening. I changed my mind when I realized that bright idea would require some serious manual research and work.
Did I give up? Of course not. I did what any good engineer would do – I found an easy (and smart) solution that did not require substantial extra effort – a bit like re-using verification ip’s instead of making them from scratch. This level of engineering genius is often mistakenly perceived as laziness, but I like to call it being smart. In fact I recently wrote a blog on the topic of working smart not hard.
For the rest of this article, visit the Aldec Design and Verification Blog.
Much has changed in the last 30 years
Friday, January 10th, 2014
When I first launched Aldec in 1984, home computers hadn’t quite taken off and innovations such as the compact disk and those oversized, power draining cellphones were still struggling to obtain mass acceptance.
Fast forward 30 years, even those of us in the electronics industry have whiplash from the speed at which technology is advancing and delivering new products. Buyers are more eager to become early adopters of innovative new technology, and smarter, faster tools are required to keep pace.
As a long-time member of the Electronic Design Automation (EDA) community, Aldec has had a front row seat to the technology race and over the years we have celebrated many successes of our own. Here, our product managers reflect on some of our most memorable highlights from 2013.
