Posts Tagged ‘dac’
Thursday, August 22nd, 2013
Dr. Benjamin Carrion Schafer, Assistant Professor at Hong Kong Polytechnic University (and longtime fan of Aldec’s latest offering, CyberworkBench from NEC) was kind enough to author a guest blog for Aldec. Here’s an excerpt:
My first encounter with NEC’s CyberWorkBench (CWB) was in 2003 while attending DAC. Like most people, I was surprised to see a big Japanese company offering EDA tools. NEC is definitely known more for its consumer products and telecommunication equipment. I have to admit, the main reason I stopped at their booth – was that they had hired a magician.
This magician told the audience he would teach us a trick and give us a set of magic cards if we stayed until the end of the presentation. I did and I received my set of magic cards (which I still keep). At the same time I also became a CWB user and even wound up working for NEC.
As an assistant Professor at the Hong Kong Polytechnic University, I currently teach advanced VLSI courses and use CWB. It has some amazing capabilities. Let’s start with the fact that it supports ANSI-C and SystemC. Although SystemC might be a step in the right direction to have a unique standardized IEEE language, supported by all main HLS tools, it is not very intuitive and takes some time to master (especially if the user does not have a C++ background). Here is where ANSI-C support becomes very handy. Most people do know ANSI-C and it is very straightforward to convert any ANSI-C SW description into synthesizable C code.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Aldec, ansi-c, c/systemc code, dac, design, distributorship, hls, ide, nec cyberworkbench, qor visualization tool, rtl simulation, SoC, SoC and ASIC Prototyping, systemc, Validation, verification, verification process
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Tuesday, June 11th, 2013
Functional Verification Insights from Austin
I just returned back to the office from the 50th Design Automation Conference (DAC) which took place in Austin, TX, on June 2—6. As I began compiling my trip report, I thought that I might share some of my observations, especially for those who couldn’t attend this industry event but still wanted to gain some insight.
Conference itself
One of the reasons I like DAC is that it has always been the main industry event, attracting people from all over the world, and provides participants with the opportunity to meet most of their key customers, ecosystem partners, and competitors in a single location. From an exhibitor’s perspective, DAC is mainly about engaging with attendees on the floor, learning about their current and anticipated challenges, and educating them on how they can innovate and succeed using our product offerings.
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Tags: cdc, dac, design automation conference, driver software verification, ecosystem partners, fpga-based prototyping, Functional Verification, high level synthesis, hls, hw/sw co-verification, mixed-signal simulation, multimillion gate soc, multiple clock domains, Riviera-PRO, SoC, SoC and ASIC Prototyping, SoC Verification, spec-tracer, system development, system verilog, systemverilog-based uvm, uvm-compliant environments, verification, verification ips, vips
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Thursday, May 30th, 2013
Free DAC INSIGHT Presentation
 At the fast-approaching Design Automation Conference (DAC) 2013 in Austin, TX, Aldec will co-host an INSIGHT Session with Agilent Technologies on how to validate a digital signal processing algorithm for both floating and fixed point levels. As Riviera-PRO Product Manager, I will join Agilent Senior Product Marketing Engineer FAE, Sangkyo Shin, on Wednesday, June 5th at 2pm in presenting a combined Agilent/Aldec FPGA flow that can be used to quickly validate communications digital signal processing (DSP) algorithms and accelerate physical layer (PHY) performance measurements.
  Mr. Shin will review the system-level design challenges and how to solve them using the SystemVue™ software, which provides the capabilities needed to evaluate and design modern communication systems and related products. I will then take the auto-generated HDL code from a system-level concept down to HDL simulation in Aldec Riviera-PRO™ and FPGA implementation on Aldec HES-5™ hardware prototyping board. Attendees will gain valuable insight on the cross-domain approach to traditional FPGA design flow and learn how to validate FPGA design for leading edge wireless and radar system with a system-level simulation tool integrated into the traditional hardware design flow.
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Tags: accelerate physical layer phy performance measurements, agilent, Aldec, aldec hes 5 hardware prototyping board, dac, debugging, dsp algorithms, FPGA, fpga design flow, hardware design flow, hdl debugging tools, hdl simulation, Riviera-PRO, riviera-pro product manager, systemvu software, validate communications digital signal processing, validate design, wireless algorithm validation
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