Posts Tagged ‘acceleration’
Tuesday, August 11th, 2020
 In the early days of digital design, all circuits were designed manually. You would draw K-map, optimize the logic and draw the schematics. If you remember, we all did many logic optimization exercises back in college. It was time consuming and very error prone. This works fine for designs with a few hundred gates, but as the designs get larger and larger this became non-feasible.
Designs that are described at a higher level of abstraction are less prone to human errors. High-level descriptions of designs are done without significant concern regarding design constraints. The conversion from high-level descriptions to gates is done by using synthesis tools. These tools use various algorithms to optimize the design as a whole. This circumvents the problem with different designer styles for the different blocks in the design and sub-optimal design practices. Logic synthesis tools also allows for technology independent designs. Logic synthesis technology was commercialized around 2004, and since then it’s been part of the standard EDA tool chain for ASICs and FPGAs.
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Tags: acceleration, Active-HDL, design, embedded, Emulation, FPGA, FPGA Simulation, HDL, HES-DVM, Intel, Synthesis, systemverilog, verilog, Xilinx
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Wednesday, February 28th, 2018
When should we use the term “Vision for Everything”, as vision-based applications are entering various industries? It’s been a few years since the emergence of Embedded Vision and we see that it’s being used in a wide range of applications including Security, Medical, Smart homes, Robotics, Transportations, Automotive Driver Assistance Systems (ADAS) and Augmented Reality (AR).
This is the first in a series of blogs explaining what you need to know to start designing Embedded Vision applications which can be used in ADAS, from choosing the right device and tools to demystifying the vision algorithms used in automotive applications and how to implement them into FPGAs.
ADAS consists of two main parts, vision and sensor fusion. Cameras used in a smart car can provide the information such as object detection, classification and tracking. However, they don’t provide the distance between the vehicle and obstacles needed to prevent a collision. To do that, sensors such as LIDAR or RADAR come to play.
In this series of blogs, we will mainly focus on the vision side of the ADAS; but will cover sensor fusion in the future. The main goal of this series of blogs is to give an in-depth knowledge of Aldec’s complete ADAS reference design which includes 360-Degree Surrounding View, Driver Drowsiness Detection and Smart-Rear View.
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Tags: acceleration, ARM, embedded, FPGA, hardware, verilog, VHDL, Xilinx
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Thursday, January 25th, 2018
 A high-performance router is an absolute must if you want to run a high-traffic network in which different devices need to transfer and receive data as fast as possible. A router with a powerful processor and sufficient local memory reduces data hiccups and minimizes message loading and buffering times. But is that enough?
Because of the huge amount of data that people now generate – combined with the wealth of communication protocols, such as Wi-Fi, Ethernet, USB, SFP, QSFP – high-performance, hardware re-programmable routers are becoming popular. That hardware re-programmability is being delivered through FPGAs, and utilizing one as the main ‘processor’ on the router makes it easy to add or modify desired modules such as encryption and compression.
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Tags: acceleration, design, digital, embedded, Emulation, FPGA, hardware, industrial, prototyping, SoC, SoC and ASIC Prototyping, Xilinx
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Friday, August 11th, 2017
 FPGA Design Verification Challenge
The FPGA design and verification “ecosystem” changes rapidly to keep pace with the fast growing size of FPGA devices. The largest Xilinx Virtex UltraSCALE chips provide 4.4 Million logic cells or using another metric 50 million equivalent gate count.
To enable efficient design process for Virtex-7 and newer UltraSCALE FPGAs, Xilinx provides software called Vivado Design Suite. Besides supporting a classical HDL design flow, it also provides system level design tools like IP Integrator, System Generator or even High Level Synthesis, that are very convenient for designing large and complex designs.
Verification has always taken a significant share of the project schedule with HDL simulation being the main stage of that process. With such big designs however, even the fastest simulators would spend hours in simulation tasks.
Simulation Acceleration with HES-DVM™
Aldec’s HES-DVM bridges this gap enabling accelerated simulation with the design running in the FPGA and the testbench in the simulator.
Aldec has been providing HES™ – Hardware Emulation Solutions since 2001. During that time the HES evolved to address the most sophisticated design requirements and fulfill customers’ requirements. Thus, simulation acceleration is only one example of how HES can be used with other applications being hybrid co-emulation, in circuit emulation, and physical prototyping.
With simulation acceleration the user can move any synthesizable module from simulator to the FPGA thus offload some processing from the HDL simulator. Typically, an entire design is implemented in HES board and the simulator only executes the testbench.
Figure 1: Signal-level simulation acceleration
The HES boards are seamlessly integrated with the simulator with PCI Express x8 physical connection to the host workstation. The HES-DVM provides co-simulation interfaces for Aldec’s Riviera-PRO and Active-HDL simulators but also for other 3rd party simulators. It can be used both in Linux and Windows operating systems with all required PCIe drivers and interfaces working out of the box.
The DVM tool automates the process of design compilation and implementation for HES boards. It generates all necessary scripts and configuration files to run simulation acceleration in a given HES board but also brings many useful debugging features. Despite running your design in FPGA hardware you can keep simulation level visibility with an RTL View of all internal probes.
Figure 2: Design setup flow for acceleration using DVM™
Acceleration Benchmark
MIG controller for DDR3, AXI interconnect, two AXI traffic generators and one AXI protocol checker as shown in the following diagram.How much acceleration can I achieve? This is always the first customer’s question and frankly there is no straight answer because the result depends on the complexity of both the design and the testbench. Usually a good estimation can be obtained from running simulation profiling and then applying Amdahl’s rule. However, the best way to verify acceleration potential is just to experiment with a typical design, so we have created a simple design of a memory sub-system using Xilinx Vivado Design environment. It contains MIG controller for DDR3, AXI interconnect, two AXI traffic generators and one AXI protocol checker as shown in the following diagram.
Figure 3: Diagram created for memory subsystem benchmarking
Benchmark Results
Workstation and software used for benchmarking:
Workstation:
CPU: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz
RAM: 32 GB
HES Board: HES7XV4000BP_REV2, contains 2x Virtex7 2000 FPGA
Software:
OS: Linux CentOS 6, x86_64
Simulator: Riviera-PRO 2017.02
Design env: Vivado 2016.4
Acceleration env: HES-DVM 2017.02
If you are interested in further details about this project, benchmark, and tools which can significantly accelerate your simulation you can view the following application note: https://www.aldec.com/en/support/resources/documentation/articles/1915
Tags: acceleration, co-simulation, FPGA, HES-DVM, simulation, SoC and ASIC Prototyping, verification, Xilinx
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Tuesday, May 10th, 2016
 Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability of FPGAs have increased, however, the distinction between FPGA and ASIC design has narrowed. A modern FPGA verification flow looks very much like an ASIC verification flow.
Small and large fabless companies alike need a reliable verification partner that suits their budgets while still providing a high level of support. To answer the call, we at Aldec have extended our spectrum of verification tools for use in digital ASIC designs.
A Basic ASIC Verification Flow
Managing verification for ASICs requires a well-defined verification plan. Efficient verification planning starts with functional and design requirements in which requirements are mapped to verification methods, scenarios, goals and metrics, coverage groups, and results. Mapping entails traceability throughout the project that must be well maintained so that changes in the requirements will seamlessly reflect potential changes downstream to the elements of the verification plan.
While traceability can benefit any design, it is mandatory for safety-critical designs regulated by standards such as ISO-26262 for automotive, IEC-61508 for industrial and DO-254 for avionics.
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Tags: acceleration, asic, Emulation, linting, prototyping, simulation, SoC and ASIC Prototyping, verification
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Wednesday, April 6th, 2016
Doulos CTO, John Aynsley, and I will be presenting a free 1 hour training webinar, Acceleration-Ready UVM, on Wednesday April 13th, 2016. Learn more in this guest blog by John Aynsley, excerpted from the Aldec Design and Verification Blog.
Acceleration-Ready UVM
by Doulos CTO, John Aynsley
We hear that emulation is one of the fastest-growing segments in EDA right now, yet simulation still continues to be the main workhorse for functional verification, and SystemVerilog and UVM are everywhere you look. But how do you combine the two? How do you run a UVM-based constrained random verification environment alongside an emulator and get reasonable execution speed?
Many vendors have solutions, including Aldec with their HES-DVM™ emulator. Their solution is based on the Accellera SCE-MI standard, and in particular on SV-Connect, which is a function-based interface that uses the SystemVerilog DPI (Direct Programming Interface) to pass information between the host and the emulator. You partition your UVM drivers and monitors into two parts, a small proxy that remains on the host and a synthesizable implementation that goes into the emulator. That way, all of the low-level timing detail is removed from the UVM code running on the host and is placed in the emulator, where it belongs. The communication between the host and the emulator can be optimized to avoid the emulator being stalled while waiting for the slower UVM simulation running on the host.
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Tags: acceleration, Emulation, hardware, systemverilog, uvm, verification
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Friday, January 22nd, 2016
 I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices with ViewDraw schematics required many hours in front of a terminal. Fast track to today’s advances such as Xilinx UltraScale and Vivado HLx, and I hope you would agree things have moved on quite a bit.
Amid all this changes, however, there are some things that have remained constant. Those are the three things that are great about FPGAs: they are reprogrammable, reprogrammable, and, they are reprogrammable!
So how is this capability utilized? Here are three examples:
Electronic products using FPGAs:
I think it is important not look at FPGAs as some poor cousin of an ASIC. This view is from the days of LSI Logic and Xilinx marketing battles, when FPGAs were used for mopping up “glue logic”. Today an FPGA provides a massively parallel programmable digital platform with a lot of silicon IP, such as high-performance interfaces. This capability is widely used by many industries now; it is not solely driven by the volume of parts. Today, you even find FPGAs in consumer products.
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Tags: acceleration, asic, embedded, FPGA, hardware, project management, university, verification, Xilinx
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Wednesday, July 24th, 2013
 Breaking the Bottleneck of RTL Simulation
Utilizing hardware acceleration in a System-on-Chip verification cycle can speed-up HDL simulation runs from 10-100x, while providing the robust debugging available from an RTL simulator. Acceleration (also referred to as Co-Simulation) combines the speed of FPGA-based prototyping boards, by offloading resource hungry modules into the FPGA, while non-synthesizable constructs of the testbench remain in the RTL simulator.
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Tags: acceleration, Aldec, asic gates, FPGA, fpga boards, fpga-based prototyping boards, hardware acceleration, Hardware Emulation, HDL, hdl simulation, hes design verification manager, HES-DVM, Riviera-PRO, rtl simulator, soc design, system-on-chip verification cycle
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Thursday, May 16th, 2013
 This year’s Design Automation Conference (DAC) will be held in Austin, Texas. If we survive the 70% humidity, our team looks forward to meeting you at Booth #2225 from June 3-5. Aldec HQ is located in Nevada just outside of Las Vegas… so we’re accustomed to more of a dry heat.
We invite you to register at www.aldec.com/dac2013 to attend a technical sessions led by Aldec’s top engineers from all over the world. I can’t stress enough how important it is to pre-register since these sessions do fill up quickly. You’ll also get a free t-shirt when you attend one of our sessions – we’ve designed some pretty cool ones to give away this year.
Aldec has also teamed up with Agilent to deliver a DAC Insight Presentation on Wireless Algorithm Validation Wednesday, June 5, 2013 from 2:00-4:00pm. Learn more.
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Tags: acceleration, asic, design, DO-254 Compliance, Emulation, FPGA, FPGA Design, Functional Verification, HES, HES-7, require life cycle management, SoC, SoC and ASIC Prototyping, specialized application
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In the early days of digital design, all circuits were designed manually. You would draw K-map, optimize the logic and draw the schematics. If you remember, we all did many logic optimization exercises back in college. It was time consuming and very error prone. This works fine for designs with a few hundred gates, but as the designs get larger and larger this became non-feasible.
