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Thursday, September 14th, 2017
Tags: Accelerator coherency port, ARM, AXI interconnection, AXI Lite, AXI memory map, AXI stream, embedded, FPGA, General purpose interface, High Performance interface, SoC, TySOM, Xilinx, Zynq
1 Comment »
Wednesday, August 2nd, 2017
Tags: aldec spectracer, DO-254 Compliance, do-254/cts, requirements management tool, source code parser, spec-tracer, Traceability, traceability data, traceability matrix
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Thursday, June 15th, 2017
Tags: Active-HDL, Emulation, FPGA-based hardware emulation platform, hardware, Hardware Emulation, HES-DVM, mixed language simulations, SoC and ASIC Prototyping, system c, system verilog, utilise Virtex-7, verilog, VHDL, Virtex UltraScale FPGAs, Virtex-7
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Thursday, June 1st, 2017
Tags: Active-HDL, ARM, asic, FPGA, FPGAs embedded processors, Hardware Emulation, Hardware-Assisted Verification, high level synthesis, RTL simulator kernel efficiency, SoC and ASIC Prototyping, soc design verification, verification
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Monday, April 10th, 2017
Tags: Active-HDL, ARM, asic, co-simulation, design, FPGA, fpga prototyping solution, hardware, prototyping, SoC, SoC and ASIC Prototyping, soc design, Xilinx
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Monday, November 14th, 2016
Tags: Active-HDL, AXI, FPGA, fpga acceleration, fpga technology aldec, high level synthesis, hpc platform, LUTs, matlab coder, parallel GPU programming, PCI Express, Riviera-PRO, rtl, simulation, synchronization, Virtex-7, Virtex-7 architecture, vivado high-level synthesis, Vivado HLS, Vivado HLx Editions, Xilinx Virtex-7 FPGA
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Monday, November 14th, 2016
Tags: Active-HDL, debuggability, extendibility, fpga designers, fpga vhdl verification, hw designers, maintainability, modifiability, overview, readability, reusability, Riviera-PRO, simplicity, sw designers, testbenches, uvvm
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