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Beer, Cars, and Verification. My thoughts after DVCon Europe

Wednesday, November 9th, 2016

Tags: Active-HDL, Aldec, bus functional model, dvcon, fpga vhdl verification, uvvm, vhdl europe
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FPGAs Accelerating IoT Gateway and Infrastructure Tiers

Tuesday, October 4th, 2016

Tags: Active-HDL, fpga acceleration, FPGA Design, internet of things, programmable soc, SoC and ASIC Prototyping, tysom board, tysom gateway, xilinx zynq soc
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It’s Time to Get Your University in Sync with Zynq: Insight From a College Student

Wednesday, August 17th, 2016

Tags: Active-HDL, Aldec, embedded, FPGA, Xilinx, Zynq
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Introduction to AXI Protocol: Understanding the AXI interface

Wednesday, August 17th, 2016

Tags: Aldec, ARM, embedded, TySOM
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The UVM Configuration Database

Tuesday, May 31st, 2016

Tags: Riviera-PRO, simulation, uvm, verification
1 Comment »

Vegetarian Dining in Austin – DAC 2016

Tuesday, May 31st, 2016

Tags: asic, Emulation, SoC and ASIC Prototyping, verification
1 Comment »

The hardest part of DO-254 is…

Monday, May 23rd, 2016

Tags: do-254, FPGA, safety-critical, SoC and ASIC Prototyping, Traceability, verification
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To Emulate or Prototype?

Monday, May 23rd, 2016

Tags: Emulation, FPGA, prototyping, SoC and ASIC Prototyping, Xilinx
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UVM Register Layer: The Structure

Wednesday, April 6th, 2016

Tags: simulation, uvm, verification, verilog
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Why I see C in SCE-MI

Friday, March 18th, 2016

Tags: direct programming interface, IP, sce-mi, system c, system verilog, systemverilog
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