How Can Verification IPs Help the SoC Testing Process?

How to use VIPs In Practice

Let’s assume that we are designing a new system on chip (SoC) which contains a processor and memory controller, as well as analog and digital peripherals like Ethernet, USB, 1-Wire and JTAG controllers.

Allow me to describe a typical verification process, and explain why I recommend the use of Verification IPs within the testing process.

Figure 1. Typical verification process

The first step in the verification process is simulation which allows a verification engineer to find the most obvious bugs reasonably fast. It is the easiest, most flexible and inexpensive way of verifying a design project, especially at the block level. Another advantage of simulation is the ease of use of standardized methodologies for verifying integrated circuit designs, for example Universal Verification Methodology (UVM), which is becoming more commonly used today.

Unfortunately, due to limited computing power and the growing complexity of modern designs, simulation is not fast enough for long and complex tests. It is mainly used to verify each component separately with a limited scope of tests. Simulation of the whole design would require a lot of time, even for simple test scenarios. However, design schedules can rarely be extended or prolonged, so engineers need to find a faster way to check the whole system on chip.

works. Simulating it would take too much time, so we are going to use hardware emulation instead. Fortunately, we don’t have to avoid using UVM in emulation, because well-designed transactors can be used in the same way as in simulation.

For the rest of this article, visit the Aldec Design and Verification Blog.

Tags: Aldec, Emulation, HES-7, HES-DVM, ICE, In-circuit emulation, Kamil Rymarz, Monitor, Riviera-PRO, SoC Verification, Speed Adapter, Test, Transactor, Validation, Verification IP

Categories: Emulation/Acceleration, SoC Design and Validation

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