Aldec Design and Verification
Stan has been active in Silicon Valley since 1979, tackling challenging opportunities such as start-up companies that attempted to apply emerging semiconductor technologies to solve engineering problems related to physical rehabilitation, robotics, and entertainment. Recently, he has joined the team at Aldec as Regional Account Manager to help support digital design and verification engineers with useful EDA Solutions. « Less
Stan has been active in Silicon Valley since 1979, tackling challenging opportunities such as start-up companies that attempted to apply emerging semiconductor technologies to solve engineering problems related to physical rehabilitation, robotics, and entertainment. Recently, he has joined the … More »
Are Metastability Monsters Lurking Beneath the Surface?
March 5th, 2015 by Stan Hanel
The law appears when your elegantly-sculpted hardware and artfully-styled software code bang up against the real world of transition delays and timing requirements.
Over time, designers and trouble-shooters develop a healthy respect for Mr. Murphy and begin to anticipate when he is looking over their shoulder, learning “best practices” for recurring design problems.
The toughest design problems to trouble-shoot are ones that fail intermittently. A hidden flaw seems to pop up randomly with no certain pattern or definable cause.
Digital design and verification engineers have their own intermittent “monsters” to contend with. For these engineers, navigating through metastability pitfalls is one of their most formidable challenges.
Metastability monsters hatch at the fringe of clock domains, where clean, precisely-timed and synchronous signals leave their nice safe harbors to journey over an analog ocean of randomness and risk, where hidden traps can lure defenseless signals into captive lairs.
Not all signals will reach the safety of a familiar shore. Some will lag behind and beneath the rippling waves inside their digital eco-systems.
Metastability monsters may seem benign at first, but as more complexity is added to their habitat, more opportunity arises for wayward signals to fall within their restraining nets, and the desperate need for an experienced pilot becomes obvious.
To guide these signals and help them reach the friendly shore of a reliable clock domain, Aldec offers ALINT-PRO-CDC™, a new product within the company’s ALINT™ family of “linting” tools for Design Rules Checking (DRC).
ALINT-PRO-CDC is a Clock Domain Crossing (CDC) verification solution that provides engineers with best practices for analyzing clock domain crossing behavior early in the design cycle and offers analysis derived from both static and dynamic verification techniques, to ensure reliable cross-domains interactions.
For the rest of this article, visit the Aldec Design and Verification Blog.
Category: Functional Verification