Krzysztof SzczurKrzysztof joined Aldec in 2001 and was a key member of the team that developed HES-DVM™, Aldec's FPGA-based simulation acceleration and emulation technology. He has worked in the fields of HDL IP-core verification, testbench automation and design verification for DO-254 compliance gaining practical experience and deep understanding of design verification methodologies, emulation and physical prototyping. As Hardware Verification Products Manager, Krzysztof cooperates with key customers and Aldec's R&D to overcome complex design verification challenges using Aldec hardware tools and solutions. Krzysztof graduated as M.Eng. in Electronic Engineering (EE) at the AGH University of Science and Technology in Krakow, Poland.
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Krzysztof SzczurKrzysztof joined Aldec in 2001 and was a key member of the team that developed HES-DVM™, Aldec's FPGA-based simulation acceleration and emulation technology. He has worked in the fields of HDL IP-core verification, testbench automation and design verification for DO-254 compliance gaining
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How HES™ Technology Solved Problems for These Users
October 20th, 2014 by Krzysztof Szczur
Recognizing a problem that engineers are facing and developing a solution has been Aldec’s rather straight-forward mantra for going on thirty years now. Aldec launched its Hardware Emulation Solutions (HES) product in 2003, integrating RTL simulation with hardware emulation, and offering hardware and software design teams the ability to work concurrently. Today HES™ is a fully automated and scriptable HybridVerification and Validation environment for SoC and ASIC designs capable of bit-level simulation acceleration, SCE-MI 2.1 transaction emulation, hardware prototyping, and virtual modeling.
Use Case #1 – A Fabless Semiconductor Company
In this case, the user had many requirements including the verification of a 20 million gate design in bit level acceleration and SCE-MI transaction level emulation, and also required extensive debugging functions. The verification process was performed using HES technology (DVM, transactors and HES boards) in acceleration and SCE-MI emulation with all required debugging features, memory support and Virtual Platform integration. [More Use Case Details]
For the rest of this article, visit the Aldec Design and Verification Blog.
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Tags: Aldec, automated and scriptable hybridverification, bit-level simulation acceleration, debugging, embedded, fabless semiconductor company, fpga ASIC prototypes, fpga-based emulation system, hardware emulation solutions, hardware prototyping, hes product, hes technology, hes usecases, HES-7, HES-DVM, SCE-MI 2.1 transaction emulation, sce-mi emulation, SoC and ASIC designs, SoC and ASIC Prototyping, uvm, validation environment, verification, virtual modeling
Category: SoC Design and Validation
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