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#53DAC, 7: Fly brains, trillion-transistor devices and tales from a Steve Jobs alum

Tuesday, April 26th, 2016

All of a sudden it’s nearly the end of April, high time to switch from months to weeks (just six to go now!) in the countdown to DAC, which I can guarantee is going to be a great conference. One big reason I’m confident is that, as always, we have an excellent lineup of keynoters as worthy of a stage at TED or SxSW as at the world’s premier design automation conference. See my past posts on Peter Stone (Thursday keynote) and Lars Reger (Monday) for a refresher. And don’t forget the luminaries sandwiched between the two of them:

Tuesday back-to-back big thinkers will take the main stage. One is Louis Scheffer, a researcher at Howard Hughes Medical Institute. Shcheffer has spent a lifetime studying whether it might be possible to reconstruct the nervous system, a challenge given the boggling complexity in even the simplest animals. The humble fly brain that Scheffer studies has about 100 million connections. The success of Scheffer and his colleagues in mapping a small fraction of those connections, the region of the fly’s brain that processes vision, warranted a 2013 publication in Nature, likely the world’s most prestigious scientific journal.

IP Cuts Dynamic Power Dissipation 20% More Than Can Be Achieved With Standard Techniques

Tuesday, January 26th, 2016

CC-100 PowerOp IP 

The CC-100 PowerOp IP harvests waste energy (logic overlap current) in digital and mixed signal SOC’s, and recycles a portion of it back into the system for an overall lower system power profile.  This IP allows users to save watts of power, depending on how much digital or dynamic power is being consumed in a given SOC, and can fit in the left-over “white space” of most SOC or processor designs.

In short, this IP turns the standard power saving techniques around, saving power when circuits turn on, thus complimenting, not competing with, standard industry techniques normally used to save power.

The CC-100 PowerOp IP has been realized in Proof-of-Concept silicon and has been produced and characterized on the IBM CM018RF RF manufacturing process.

The CC-100 PowerOp IP import is scalable to any IC process ranging from .6um to 28nm, available on request from CurrentRF   Proof-of-concept, characterization, and design aid documents and boards for the CC-100 IP are also available on request.


USB used as an Analog-RF Port

Tuesday, January 26th, 2016

Most associate USB and it’s hardware as a digital and system data transfer protocol only.  Thinking of USB in terms of Analog and RF has only recently been a subject of interest in USB design, a necessity with the advent of USB 3 speeds and protocols.   In fact, RF effects become dominant in the data transfer speeds involved with in USB 3.    CurrentRF has developed a methodologies and technologies that allow server and network device USB ports, normally thought as digital and system data transfer ports, to be used as Analog/RF pickup ports for system noise and power reduction.

If one opens and ignores the data lines used for any flavor of USB, and focuses only on the resident +5V power and ground lines, one will see a rich source of RF frequencies of significant magnitude, that would enable energy harvesting techniques to be employed to recover this resident, generated energy.  In fact, if one utilizes an ac coupled spectrum analyzer of sufficient bandwidth, one will not only see frequency spikes and noise related to USB data transfers, but “coupled in” frequencies and noise energies related to other aspects of servers and network devices.


Emulation Takes Center Stage

Wednesday, May 27th, 2015

Emulation is enjoying its moment in the spotlight and none too soon. Design complexity of all types has conspired to make chip verification an arduous task. These days, the fabric of system-on-chip (SoC) designs includes several processing cores, large sets of specialized IP, a plethora of peripherals and complex memories, routinely pushing the design size into the hundreds of million gates. Embedded software now exceeds the complexity of the hardware.

Consider that for each hardware designer there are at least five software developers. No surprise that chip verification and validation has become an overriding concern for all project teams, particularly when hardware and software integration is concerned. Here is where the rubber meets the road, and where the verification challenges reach their peak.


DesignCon Panel On Next – Gen Engineering has our young engineers voicing their opinion on the future of engineering

Wednesday, March 4th, 2015

DesignCon, held at the Santa Clara Convention Center, is one of the biggest annual conference on product technologies, design methodologies, and EDA software, with a focus on system-on-chip design.

IPC APEX EXPO 2015 Programs Highlight Technology and Innovation

Wednesday, December 10th, 2014

logo3No matter where you are in the global electronics supply chain, you’ve probably heard the phrase, “I need it now.” In this fast-moving, ever-evolving industry, we hear that a lot.

What drives what happens now? A critical combination of the latest technology and knowledge, which is what you’ll find at IPC APEX EXPO 2015.


Developing USB 3.1 IP? Essential Updates To USB 3.0 You Need To Know

Tuesday, November 4th, 2014


USB-3-1-vs-USB-3-Technical-ComparisonInitially, USB provided two speeds (12 Mbps and 1.5 Mbps). With rapid adoption and success of the USB standard and the increasing power of PCs and computing devices, the USB 2.0 specification was defined in the year 2000. USB 2.0 provided upto 480 Mbps of bandwidth while keeping software compatibility with earlier USB applications. With ever increasing bandwidth requirements, in 2008 the USB 3.0 specification (providing 5 Gbps bi-directional bandwidth) was released. USB 3.1 is the next logical step in this progression. It provides 10Gbps of bi-directional bandwidth while maintaining backward compatibility with previous USB versions. To know more about USB 3.1 Verification solution click here.

In this post, we will analyze the technical differences between the USB 3.1 and USB 3.0 specifications. The aim is to enable people familiar with USB 3.0 to quickly understand the main aspects of USB 3.1.

 We will analyze the PHY, Link and Protocol layers and list out the major ways in which USB 3.1 differs from USB 3.0.


Does An Externally Bought IP need Re-Verification?

Monday, October 27th, 2014

Verification is never ending process! You can never be sure that you have verified everything. The aim of verification is risk reduction to the level of practical perfection.

The increase in chip complexity coupled with pressure to shorten time to market, are pushing chip design companies towards adoption of third party IPs. Let us consider you have weighed in all pros and cons of IP outsourcing and decided have to go for a third party IP for your next project. Then the question is – Does the externally bought IP need re-verification?


Why Verification IP Switching Costs Are A Myth

Monday, October 6th, 2014

wood-cutter-200x174Many of you may have heard the story about the woodcutter and his blunt axe. The “Switching cost” of sharpening/buying a new axe may seem to be too high when in a time crunch. But a step back to review the situation and switching to a better tool can be life changing!

In today’s world this applies to chip design and verification teams more than ever. A Verification IP plays a key role in controlling verification schedules. Consider a case where tape out schedule is slipping in spite of having both – Internal VIP and External VIP.

Just like a blunt axe will take much longer to fell a tree, a sub standard Verification IP will prolong your IP Development. On the other hand if you “sharpen your axe” i.e. develop/buy a better Verification solution, it may initially seem like its taking longer and others are getting ahead. But, in the long run you will develop your IP faster.


What future for the DATE conference?

Monday, April 7th, 2014

Two weeks ago my associate and myself attended the DATE conference to meet people and try to get new leads. This year, the conference took place in Dresden, Germany, which is at the heart of the “Silicon Saxony”, with no less than 40,000 jobs mostly in the semiconductor industry, so we were expecting a lot. If you’re not familiar with the conference, according to their website, “DATE combines the world’s favorite electronic systems design and test conference with an international exhibition for electronic design, automation and test, from system-level hardware and software implementation right down to integrated circuit design.” We had high expectations, and in the end we were quite disappointed. Granted, receptions (exhibition reception and DATE party) featured very good food and the party even included a visit of Volkswagen’s awesome luxury car plant. The staff was professional and nice, and we were lucky to have a neighbor who gave us an interesting perspective and helpful advice. What about the actual exhibition?

First, DATE is not cheap. Special start-up price is 2K€ ($2.7K). I just looked up DAC, it has a special “first exhibitor” package, for a mere $1.5K. DAC is about three times bigger, too. Concerning attendance, I was able to find numbers here and on the websites for the previous editions. There were 625 exhibition visitors in 2010, increased to 890 in 2011 (probably due to the presence of GlobalFoundries), and 800 in 2012 and 2013; the number of conference attendees has been around 1,300 and now is around 1,400. I couldn’t find any other statistics. By contrast, DAC compiles in-depth statistics about its visitors, including demographics and an event audit.


S2C: FPGA Base prototyping- Download white paper

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