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#54 DAC 5: Why DAC’s a better place than ever to exhibit

Monday, March 6th, 2017

You’ll notice something different when you walk into the Exhibit Hall at the Austin Convention Center this coming June. We are very excited to be featuring new suites from Freeman, one of the most innovative event-marketing vendors around. (Seriously, they do great work; browse their site for five minutes and you’ll see what I mean.)

Here are just a few of the upgrades that are in the works:

  • Quieter booths. The Exhibit Hall can be a hive of activity with demos and in-booth presentations and giveaways. This of course generates noise, great when it comes to the general energy level and enthusiasm on the floor but occasionally challenging when it comes to having quiet 1:1 conversations. The new suite walls include hidden sound batting to help put a necessary damper on din and make it easier to talk.
  • Real doors with privacy shades. The bigger booths include improved suite rooms for private meetings. Most spaces at DAC are highly social and public so we’ve made an effort to ensure the upgraded suite rooms are as private as possible. New doors have regular door locks as you have on your office/home doors, pull the privacy shade (each door is equipped with a privacy shade) and get down to business finally landing the deal or partnership you’ve been working on for months.
  • More graphics, easier to hang monitors. Your booth first and foremost represents your brand. We all know that lots of casual conversations at DAC start with “Did you check out the booth of…?” This year it will be easier than ever to have your brand shine by adding graphics and logos to seamless tension fabric inside or outside the suites. And the wall is sturdy enough that you can quickly and easily hang monitors with some help from labor but minimum work required.

You’ll find most of the practical details on how to get started as an exhibitor here. (One pro-tip to know is that the new suites are measured in the metric system this year. I know you can handle it; we’ve been talking about nanometer-scale manufacturing process nodes forever, after. But keep that in mind when considering your floor plan, submitting materials and so on.) And you can always email Stacy Dilallo or Susie Horn, MP Associates for further information.

 

We’ve come a long way, baby! Above a DAC booth in the early 1980s.

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#54 DAC 4: DAC’s Designer and IP Tracks and the limits of social media

Friday, February 17th, 2017

When it comes keeping the growth of design productivity exponential, a key barrier that fell in the past ten years is due to the increasing use of social media, which set free the exchange of focused, expert knowledge, from user to user.  On the web we have very helpful company-curated user forums; and often even better, the stack-exchanges which are user curated, where readers up-vote the most helpful content and as a result these are often the very best place to visit to get unstuck from a problem you recognize you have.

These forums and posts are all reactions against the underfunded, or poorly directed tech publishing team, tasked perhaps by marketing (or the simple desire to keep their employment) to only document what works; and never mention an alternative solution.

Of course a web search will also take you to the swampy places where all you find is others who are stuck with similar problems, and they just bemoan that the vendor doesn’t care, or take you through a litany of things they’ve tried that didn’t work.  One also finds the beginning of tutorials, part one of what was to be a twenty volume tutorial where the blogger planned to impart the wisdom of the ages for how to build the magical thing – and only part one got written – and even that is now out of date.

So, search works great — when you have an idea what the problem is, and you are following a large crowd who has been there before, and they’ve taken the time to create hints.

 

Going hands-on at last year’s Designer/IP track session, with no marketeers in sight!

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#54 DAC 3: January deadline for Designer/IP track submissions (and Texas-isms)

Tuesday, December 20th, 2016

Designer and IP track submissions are due Tuesday, January 24. These sessions have been among the most vibrant DAC elements in recent years based on attendance and anecdotal feedback. Chuck Alpert, my predecessor as DAC chair, explained why in a post last year: “Many of these technologists come for the Designer/IP track, a marketing-free zone aimed squarely at practitioners.”

The good news is that submitting is easy. All you need to do is bang out 100 words and six slides. You can do this, people!

More good news is the excellent industry pros in charge of these tracks.

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#54 DAC, 2: Executive committee members you need to know (and your first slate of deadlines)

Thursday, November 10th, 2016

Time is the only critic without ambition. – John Steinbeck

Like many things, DAC looks decidedly different depending on where you sit, and how you experience it.  As an attendee, it’s mostly a few days at the start of every summer where you can sample some of the best technical content on the design of circuits and systems, plus get the chance to network and have some fun with a worldwide audience that spans execs to undergrads. In contrast, as a member of the executive committee, DAC is the finish line for a year-long marathon effort to bring the best content, speakers and papers all together in one place and time, building on what works and improving where we can.

Now is the time for a reminder that if you want present a paper at DAC (especially a research paper), the 12-month calendar matters for you as well. Abstracts are due Nov. 15; manuscripts, Nov. 22!       ­

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#53DAC, 7: Fly brains, trillion-transistor devices and tales from a Steve Jobs alum

Tuesday, April 26th, 2016

All of a sudden it’s nearly the end of April, high time to switch from months to weeks (just six to go now!) in the countdown to DAC, which I can guarantee is going to be a great conference. One big reason I’m confident is that, as always, we have an excellent lineup of keynoters as worthy of a stage at TED or SxSW as at the world’s premier design automation conference. See my past posts on Peter Stone (Thursday keynote) and Lars Reger (Monday) for a refresher. And don’t forget the luminaries sandwiched between the two of them:

Tuesday back-to-back big thinkers will take the main stage. One is Louis Scheffer, a researcher at Howard Hughes Medical Institute. Shcheffer has spent a lifetime studying whether it might be possible to reconstruct the nervous system, a challenge given the boggling complexity in even the simplest animals. The humble fly brain that Scheffer studies has about 100 million connections. The success of Scheffer and his colleagues in mapping a small fraction of those connections, the region of the fly’s brain that processes vision, warranted a 2013 publication in Nature, likely the world’s most prestigious scientific journal.
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IP Cuts Dynamic Power Dissipation 20% More Than Can Be Achieved With Standard Techniques

Tuesday, January 26th, 2016

CC-100 PowerOp IP 

The CC-100 PowerOp IP harvests waste energy (logic overlap current) in digital and mixed signal SOC’s, and recycles a portion of it back into the system for an overall lower system power profile.  This IP allows users to save watts of power, depending on how much digital or dynamic power is being consumed in a given SOC, and can fit in the left-over “white space” of most SOC or processor designs.

In short, this IP turns the standard power saving techniques around, saving power when circuits turn on, thus complimenting, not competing with, standard industry techniques normally used to save power.

The CC-100 PowerOp IP has been realized in Proof-of-Concept silicon and has been produced and characterized on the IBM CM018RF RF manufacturing process.

The CC-100 PowerOp IP import is scalable to any IC process ranging from .6um to 28nm, available on request from CurrentRF   Proof-of-concept, characterization, and design aid documents and boards for the CC-100 IP are also available on request.

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USB used as an Analog-RF Port

Tuesday, January 26th, 2016

Most associate USB and it’s hardware as a digital and system data transfer protocol only.  Thinking of USB in terms of Analog and RF has only recently been a subject of interest in USB design, a necessity with the advent of USB 3 speeds and protocols.   In fact, RF effects become dominant in the data transfer speeds involved with in USB 3.    CurrentRF has developed a methodologies and technologies that allow server and network device USB ports, normally thought as digital and system data transfer ports, to be used as Analog/RF pickup ports for system noise and power reduction.

If one opens and ignores the data lines used for any flavor of USB, and focuses only on the resident +5V power and ground lines, one will see a rich source of RF frequencies of significant magnitude, that would enable energy harvesting techniques to be employed to recover this resident, generated energy.  In fact, if one utilizes an ac coupled spectrum analyzer of sufficient bandwidth, one will not only see frequency spikes and noise related to USB data transfers, but “coupled in” frequencies and noise energies related to other aspects of servers and network devices.

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Emulation Takes Center Stage

Wednesday, May 27th, 2015

Emulation is enjoying its moment in the spotlight and none too soon. Design complexity of all types has conspired to make chip verification an arduous task. These days, the fabric of system-on-chip (SoC) designs includes several processing cores, large sets of specialized IP, a plethora of peripherals and complex memories, routinely pushing the design size into the hundreds of million gates. Embedded software now exceeds the complexity of the hardware.

Consider that for each hardware designer there are at least five software developers. No surprise that chip verification and validation has become an overriding concern for all project teams, particularly when hardware and software integration is concerned. Here is where the rubber meets the road, and where the verification challenges reach their peak.

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DesignCon Panel On Next – Gen Engineering has our young engineers voicing their opinion on the future of engineering

Wednesday, March 4th, 2015

DesignCon, held at the Santa Clara Convention Center, is one of the biggest annual conference on product technologies, design methodologies, and EDA software, with a focus on system-on-chip design.
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IPC APEX EXPO 2015 Programs Highlight Technology and Innovation

Wednesday, December 10th, 2014

logo3No matter where you are in the global electronics supply chain, you’ve probably heard the phrase, “I need it now.” In this fast-moving, ever-evolving industry, we hear that a lot.

What drives what happens now? A critical combination of the latest technology and knowledge, which is what you’ll find at IPC APEX EXPO 2015.

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S2C: FPGA Base prototyping- Download white paper



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