Posts Tagged ‘Lee PR’
Wednesday, February 26th, 2014
Retired senior vice president of Si2, Sumit DasGupta, imparts his sage view on what the semiconductor, EDA and IP industries should focus on to ensure a vibrant semiconductor industry for 2014.
“As the new year rolls out, there are promises and associated challenges that the semiconductor industry faces that need attention to ensure the vibrancy of the industry, even as the industry struggles to stay on the Moore’s law trajectory.
First in my list is the area of 2.5D and 3D integration, an area of great promise but with significant challenges. Much has been touted about these approaches as ways to deliver “More than Moore” but it appears to this observer to be advancing at a pace that is slower than hoped for. It seems to be just another year away from full production. But now, enough said, 2014 needs to be the year when much greater focus must be applied to get at least 2.5D technology into mass production. This is not a transitory approach to 3D but rather should last longer in its own right as a very viable technology sitting alongside 3D as 2 approaches to semiconductor integration. 3D still has challenges to be addressed but here again, greater focus needs to be applied to ramp up to full production in 2015.
Wednesday, February 19th, 2014
Bob Smith, Senior VP Marketing & Business Development at Uniquify, shared with us his predictions for semiconductor IP in 2014.
“If 2014 has a watchword for the Semiconductor Industry, it would be momentum and that would be a result of the rapidly increasing use of IP in SoC designs. Add on the mushrooming need for ‘adaptive’ IP to mitigate timing and variation challenges in complex SoCs as performance issues multiply and process geometries shrink.
Moves within the DDR memory space continue to rock the industry and create momentum. Designers are heading directly to the latest JEDEC standard LPDDR4 (low-power DDR4) and moving beyond (or even skipping) LPDDR3 because they’re getting greater gains in performance and low power, an important consideration for mobile applications.
Wednesday, February 12th, 2014
Bryon Moyer, Technology Editor at EE Journal, weighs in on what the chip industry needs from EDA and IP in 2014.
“At the low level, this is going to be the year where the push and pull between EDA companies and users determines how easy FinFETs are to design with.
At the high level, it feels to me like IP and EDA need to come closer together. For years, logic design has been done using text because higher-level languages allow better design abstraction and productivity for hand-crafted designs than prior schematic approaches did. When IP entered the scene, designs were mostly hand-done, with occasional bits farmed out to IP. But now IP dominates, whether internal or third-party. Rather than having a custom-logic paradigm that accommodates IP, it feels like we need to move more to an IP paradigm that accommodates custom logic. And it’s not just about logic either: mixed signal is everywhere, and should be included more seamlessly.”
Sunday, February 9th, 2014
Next up is Brian Bailey, Technology Editor/EDA, for Semiconductor Engineering, who has shared his forecast for EDA in 2014.
“Over the next couple of years there will be an increase in ASIC starts, but not all of these will be for the latest technology nodes or be the massive chips we have come to expect. The new starts will be smaller chips that form the leaves of the Internet of Things, things such as sensors with small amounts of processing and communications. They will be targeting older processes, such as 90nm. Margins on these devices will be slim but volumes high. I see the designers of these products requiring a different mix of capabilities in their EDA tools and different price points. It may create an interesting opportunity for the second tier EDA companies to become significantly bigger.”
Thursday, February 6th, 2014
Anindya Saha, Associate VP (VLSI) at Saankhya Labs, shares his insights on what EDA and IP vendors need to do for their users in 2014.
“Today the EDA and IP companies alike are in the race to cater to the big semiconductor players by offering the greatest IP in the latest process geometries. However, semiconductor startups, – such as Saankhya – do not change process nodes very quickly because it may not necessarily make business sense. Here is why.
‘Process design margins’ is a fact of life, which we need to add when we use the latest process nodes. Incorporating these design margins simply adds to the overall SoC design cycle time which we want to keep to a minimum. Hence staying with the older process nodes may be a more prudent choice. When we look at the IP domain, we can categorize the available IPs into the following buckets – Analog IPs, Standard Cell and Memory IPs, Processor Soft Cores and Connectivity IPs. Besides the usual PPA (Power, Performance and Area) metrics, what we look at for each of these categories is the metric of Power Efficiency. This metric can be based on mW/Mhz or in some cases mW/sq. mm depending on the kind of tradeoffs which we intend to do at System level.
The following are some of the issues I feel EDA and IP companies should address, especially in the domain of standard cell and memory IPs which are commonly used in almost all ASIC Designs today. (more…)
Monday, February 3rd, 2014
Robert Beanland, Senior Director, Corporate Marketing at Atrenta, weighed in on what EDA and IP vendors need to do in 2014.
“Ahhh, the age old question of, ‘What does EDA and IP need to do this year?’ Well, …
The IP folks need a way to provide fully validated IP to their customers with not only a good understanding of all the validation that has been done, but also the expected use model and configurations for the IP. The use model is critical because it is quite common for IP to be ‘abused’ in a way or mode that the IP vendor never expected. When this happens, the customer must be able to assess the problem in-situ and work with the IP vendor to find a resolution. A standardized quality metric is much more desirable than the current option of comparing each vendor’s unique assessment of their validation. This validation and analysis should include, but is not limited to, power, clock domains, testability and physical. The ‘clean’ IP can then be used with more confidence by their customers in their SoC integration.
Wednesday, January 29th, 2014
Next up in our series is Simon Bloch’s forecast for 2014. Simon is Sr. Director of Samsung Electronics R&D, in mobile consumer wireless devices.
“The future of electronics is looking bright! Market forecasters predict growth in literally every category of electronic markets ranging from smart mobile and wearable devices, appliances and sensors connected to a network of Internet of Everything to smart connected cars and cities.
In today’s electronics products, sophisticated hardware is becoming insufficient for product success. Many layers of stacked software control the underlying hardware and determine a product’s competitiveness via functionality, performance, power and cost. And while there is always going to be a need to create new semiconductor components and IC companies will need EDA tools, EDA vendors need to expand the view of Electronics and treat software stack as an integrated part of EDA.
There are many opportunities to come up with products in the software stack space around Linux/Android operating systems and in the area of hardware virtualization. Just last month, CyanogenMod, a company that provides Android based software widely used in the mobile industry, secured $23 million in funding from top tier VCs. CyanogenMod is a software stack product and contains many features not found in Google versions of the operating system.
Monday, January 27th, 2014
We asked Mike Gianfagna, VP of Marketing at eSilicon and former VP of Corporate Marketing at Atrenta, about EDA, IP and the chip industry in 2014.
Ed: What does EDA and IP need to do in 2014?
Mike: Work more effectively with each other. IP integration continues to be a huge bottleneck for SoC design. A more uniform quality metric and a way to enforce it is desperately needed. This problem can’t be solved in isolation. EDA and IP companies need to collaborate to tame this issue. They can do it.
Ed: What does the chip industry want from EDA and IP in 2014?
Mike: The same thing really. Every SoC project is dependent on somebody’s IP. Whether it’s internally supplied or provided by your favorite IP supplier or your favorite ASIC supplier, the requirement for easy integration with no surprises is the same. Better collaboration between members of the SoC supply chain will definitely help.
Sunday, January 19th, 2014
Next up in our series of 2014 forecasts we have the sage predictions of Angel Orrantia, Business Development Director at SKTA Innopartners LLC….
“Aside from some massive players, the rest of the chip industry has been forced to adopt capital light business models. Simultaneously, we’re seeing the mask costs making advanced nodes prohibitively expensive.
Tuesday, January 14th, 2014
Back in December, Liz and I figured that it’d be a good time to ask chip and EDA/IP industry folks:
1) what will chip companies need from their EDA/IP vendors in 2014
2) what will we see develop in EDA/IP in 2014?
We thought that Jim Hogan could probably respond to both questions. He did us one better…he provided the context for us to ask these questions. While he has advice for the chip and EDA/IP vendors, what’s compelling is what Jim sees as driving design trends.
What does Jim see coming up, starting in 2014? First off, for a variety of economic reasons, he sees a lot more money becoming available for R&D. What are some of those economic dynamics? The US will become a larger oil producer than Saudi Arabia by 2020 (or maybe as early as 2015) and entirely oil-self-sufficient by 2020. Oil will become a lot cheaper as a result and the US will swing a current $1.5T deficit into a $500B one.*