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Posts Tagged ‘IP’

GABE on EDA

Tuesday, August 23rd, 2011

I recently chatted with Gabe Moretti, editor-in-chief of GABE on EDA, where he shared some of his thoughts on the business of EDA and EDA publishing.

 

Liz: You weren’t always in publishing.  You have over 30 years in EDA tool development, along with EDA senior management roles.  Then you went into electronics editorial.  You’ve written for many of the surviving publications.  If I remember correctly, you were at EDN, EE Times, EDA Café, DACazine.   Why did you go into electronics editorial?

Gabe: After Mentor acquired VeriBest there was no immediate open position at Mentor that satisfied my career goals, so I left.  I could then re-evaluate my role within the industry and try something new.  EDN convinced me that I was the person they were searching for to cover EDA.  It sounded like a good opportunity to try something new and something that would have very little negative impact on my career in the short term if I were not successful.  That was eleven years ago, and I am still doing it, albeit in a very different way.   At EDN I was a full time employee.  All the other “jobs” were actually consulting assignments.  DACezine was a very interesting experiment that did not last because the DAC executive committee that changes every year never found a fiscal model for the publication.

Liz: What led you to publish your own?

Gabe: As you know the publishing industry is going through a revolution.  Before the introduction of “social media” a relatively small number of chosen professionals were the source of information and editorial.  They were employees of corporations with a tradition in print media that were very able to generate a profit from the industry.  The on-line publishing world has radically changed that, and publishing corporations are still struggling to understand the profit making mechanism, assuming there is one.

So I decided to try a new model and see how it compares with the rest.  It is actually too soon to know, but I think it is worth the investment.  I believe that one thing is already proven: on line publishing cannot sustain the organizational overhead that print publishing has.

Liz: Tell us a little bit about GABE on EDA.

Gabe: GABE on EDA is my umbrella business, and my main web page.  At this point there are three separate ventures under it.  One is EDAMarket, the model I referred to in my previous answer.  EDAMarket is an experiment in financial terms, not in content form.  It attempts to answer the question: is there an alternative to advertisement sales (sponsorships are just another form of advertisement) to support an information channel?  I looked at selling individual subscriptions, but in an environment where distributing copies of copyrighted material is unfortunately becoming the norm, I did not find the model compelling.  So EDAMarket is supported through an annual corporate subscription.  The corporate subscribers get privileged coverage and an alternative source to their messaging.

The newsletter Assembling The Future is the second activity.  As the name implies, the subjects covered are forward looking.  Contributions are open to anyone.  Present conditions are only taken as the starting point for a projection of what the industry needs and were it can be in the next five years.

The third activity is my consulting.  At this point it is still in the startup phase, but I hope to grow it.  It will be my channel to more directly impact the progress in our industry.

Liz: What is the focus of your consulting business?

Gabe: I am helping companies with strategic marketing plans and tactical product positioning.

Liz: What is unique about GABE on EDA, and who is your target audience?

Gabe: Even when I was in charge of engineering projects I always had an eye toward the business aspect of the project.  After all, I chose engineering because it was a more secure avenue to a US citizenship than finance.  Luckily I have found that I can be successful doing a number of things.  GABE on EDA takes advantage of my business degree, my Computer Science degree, and my training in writing (thanks to attending Italian schools that emphasized composition and independent thinking).

I think that the uniqueness of GABE on EDA rests on its target audience.  My readers are executives and senior management professionals, as well as designers that are interested in the business aspect of their industry.  I am a firm believer that methods are more important than tools, and that tools are developed and sold in order to generate a profit.

Liz: You’ve been witness to a lot of change in the EDA publishing industry.  What direction do you think EDA & IP media will take?  In 5 years?  10 years?

Gabe: As I said before this is a difficult question to answer.  I think that the final choice will rest on the quality of the content developed within a specific financial model.  The audience, after all, is interested in information, not data.  Too often we confuse the two and equate data to information.  Although reliable and accurate data is necessary to generate information, the latter is the more valuable commodity in a world that is increasingly competitive and short of time.

Liz: I think we do equate data and information.  How do you define each of them and can you explain the difference between the two?

Gabe: Data is a collection of raw items that require analysis in order to become information.  As an example data is: there has not been any hurricane in Florida since 2004.  Information is: due to new weather patterns in the upper atmosphere a system of high pressure has been reasonably stationary over Florida during hurricane season, building a barrier around the region to the air movements conductive to hurricanes.

Liz: In other words, information is more than just raw data, and it is valued much more by the public if it is given with some trusted analysis.  How do you expect EDA publishing to evolve?

Gabe: I think the winning strategy will be based on the electronic delivery of information at a profit.  There is so much excitement about free stuff: open source is a perfect example of the deterioration of the capitalistic system, and the publishing world has in many ways gone open source, meaning that there are many publications, now called blogs, to choose from and almost all of them free.  Yet, authors, like engineers, need to make money to live and pursue happiness.  I think the evolution of electronic publishing will depend in large part, not from the publishing industry but from a new model of the internet that recognizes intellectual property as separate from generic data.

Liz: Speaking of delivering information for profit, what about pay for play?  What is pay for play? How close are we to total pay for play?  Is it good or bad for the industry?

Gabe: I am a bit surprised that the term “pay for play” is part of the description of a way to use electronic publishing.  Pay for play has always been around, even during the paper only era.  Certainly I experienced it since I joined the publishing industry.  To be sure some organizations, EDN for one, kept advertising separate from content generation organizationally, but you had to be a moron not to understand that subjects were covered only because they generated advertising revenue.  If you need an example close to home, look at the amount of coverage the EDA industry receives today in for-profit publications that cover the electronic industry.  Why has it gone down?  The answer you get from every publisher is: EDA vendors do not advertise.

Liz: [raises eyebrows] That’s interesting.

Gabe: Again, there must be a profit or professionals will not engage.  As long as it is understood that professional content is generated by people that are paid to communicate, the impact will be neutral.  Time is not free, and bloggers that write because they have free time to do so, are amateurs by definition, no matter how wise they might be.

I know that for some writers a blog is a powerful marketing tool: I realize that my website, is an indirect marketing tool for my consulting as well.  But that is not its primary intent.  Any of my endeavors will not survive unless they can justify themselves financially.

Liz: Likewise, where is the EDA industry itself going?  What are a couple of hot issues in our industry right now and what do you think will surface in the next couple of years?

Gabe: The major problem facing the EDA industry is the dwindling number of customers that can afford to use the latest process technology.  Manufacturing at 20nm and below is so expensive that most OEMs will choose not to use these processes.  Yet the EDA industry has been relying on its customers going from one process node to the next as clockwork to generate profits.  License renewals are fine but more expensive licenses for new tools are what keeps the industry going. EDA vendors must find a new financial model before it is too late.  By the way this new reality will also significantly impact startups.

A leading company like Synopsys, for example, will very soon have to address two very distinct markets: the leading edge OEMs producing high volume, high margin products, and the average OEMs targeting the price sensitive consumers market.  There will be producers of Ferrari like products, and KIA like products: both have a market, but they are built very differently and with different tools.  What is confusing now is that the tools look very similar, so people think they are and will be the same.  The EDA vendor that successfully realizes the distinction and serves the two market accordingly will be successful.  The PCB market is already using this model, you just have to look at Cadence that offers both Allegro and Orcad products to two very different segments of the PCB development market.

Liz: And here’s the big question…..EDA360 – what the heck is it and where is it going?  What do all of those realizations mean?….especially now?

Gabe: I am a fan of EDA360, and probably its first independent supporter, I have to admit.  This document is the first public admission that the EDA industry is at an inflection point and needs to understand some very important points.  The first one is the role that software plays and will play in future electronic systems.  I do not know the real reason John Bruggeman used in choosing the title of its document.  But I will tell you that the first picture in my mind was the IBM 360.  That mainframe revolutionized business computing both because of its hardware capabilities and its software tools.  The message of EDA360 is that our industry must not only be aware of the heterogeneous systems electronics are part of, but that it must offer application oriented solutions that make it more efficient and profitable to develop and integrate the electronics subsystem in those applications.

Liz: I see the 360 reference as meaning a complete change in thinking.  So yes, that would be revolutionary. And how do the three realizations realize these solutions?

Gabe: The “realizations” are a link to the past.  No one can build a house without foundations.  The future must be anchored to the present.  So System Realization takes an idea to a design, SoC realization transforms the design into the representation of an electronic product, and Silicon Realization prepares the product for manufacture.  Are these the same steps we will need a few years from now?  In general yes, but the contents of the steps will be different.

Liz: Anything in the offing for Gabe or GABE on EDA?

Gabe: Not immediately.  I think that EDAMarket, Assembling The Future, and my consulting activities cover the directions I would like to go.  But I am very pragmatic, so I will change as the industry changes and hopefully I will play some role in the changes, both in the publishing world and, more importantly for me, in the EDA world.

Liz: Gabe, I have no doubt that you will continue to play a vital role in delivering “information” as the EDA industry evolves.


Gabe Moretti is a recognized expert in all aspects of the EDA industry, with over thirty years of experience developing EDA tools spanning the range from design capture to chip layout. Gabe has also worked on the development of numerous industry standards and has held senior management positions with EIS Modeling, HDL Systems, and Intergraph/Veribest.  Since 2000 Gabe has been covering the EDA industry as a writer and editor first with EDN Magazine and now with GABE on EDA.

 


 

Hogan & McLellan….show you the money

Friday, May 27th, 2011

How are you going to

SHOW ME THE MONEY

In EDA?

Get the answers from noted EDA & IP investor Jim Hogan and Paul McLellan – industry pundit and editor-in-chief of DAC Knowledge Center – as they define the new path to prosperity in EDA & IP.

Jim and Paul will give a short presentation and steer an audience-oriented discussion on what direction startups and established companies in the EDA & IP space ought to steer if they want to show their investors the money.

What direction? SOC Realization…no longer just a vision.  It’s the sweet spot in EDA & IP – where to invest and where to anchor your EDA/IP startup.    So if you are contemplating starting up or re-igniting a company in the EDA & IP space, this session will help you think about how your technology will analyze and verify design concepts much earlier in the design process…at much higher levels of abstraction than before.

Where’s the opportunity? SoC Realization as a cockpit to guide a design from concept to implementation, ensuring that the design is synchronized for both the hardware and software aspects of the system’s functionality.

What’s the upshot?
These changes in the SoC Realization supply chain will alter the 1) relative values of the chain’s components and 2) ability to leverage that value into profit. SoC Realization will revalue every entity in EDA & IP – the company you want to start up, or the one you’re working for.

When: Monday, June 6, 10-11am

Where: DAC, Room 24A

Please RSVP: Liz Massingill, liz@leepr.com

For more information, contact Liz @ 831-345-4702

 

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Show me the money

Monday, May 16th, 2011

Jim Hogan & Paul McLellan challenge the EDA industry to……

Show me the money

on DAC Free Monday

 

I’m jumping up & down with excitement?   Are you? Then see details below…..

 

Who: Noted EDA & IP investor Jim Hogan and Paul McLellan – industry pundit and editor-in-chief of DAC Knowledge Center

What: Define the state and future of, and path to prosperity for EDA & IP industry.

Format will be a short presentation, then audience-oriented discussion on what direction startups and established companies in the EDA & IP space ought to steer if they want to show their investors the money.

Why: This session will help attendees think about how their companies’ technology will have to analyze and verify design concepts much earlier in the design process…at much higher levels of abstraction than before.  That’s where the money in EDA & IP will be in the coming years.

Hogan and McLellan will propose that EDA & IP companies will have to help users guide their SoC designs from concept to implementation, ensuring that the design is synchronized for both the hardware and software aspects of the system’s functionality.

What’s the upshot?
These changes in the SoC realization supply chain will alter the: 1) relative values of the chain’s components;  2) ability to leverage that value into profit; an 3) valuing of every entity in EDA & IP – the company you want to start up, or the one you’re working for.

When: Monday, June 6, 10-11am

Where: DAC, Room 24A

Please RSVP: Liz Massingill, liz@leepr.com, Lee PR

 

For more information, contact Liz @ 831-345-4702

 

 

 

 

 

What if….no more big three?

Monday, March 28th, 2011

Continuing with my conversation with Tom Kozas, president of CADmazing Solutions, I asked him about a hypothetical scenario:

 

Ed:   So Tom, what would happen if for some reason, the big three EDA vendors all went away?   So instead of Cadence, Mentor, Synopsys,  the biggest three would be Magma, Apache?  Atrenta?

Tom:  I think this raises even more questions.

Ed:  Hmmm…interesting.  What questions?

Tom:   Several come to mind:  Would this mean renewed growth for the industry? Would the fundamentals change that encourage investment in new startups? Would the design flows become more or less integrated, collaborative, and global?

Ed:  Ok, good questions to ponder.   So what would be THE big issue?

Tom:  The “Silicon” in Silicon Valley is missing.  Without investment in new semiconductor startups, growth simply won’t happen.  Virtually all new design starts are happening within the big systems and semiconductor companies which means the only way to grow an EDA company, is to steal market share.

But would this translate to increased value for the remaining EDA companies in the eyes of the financial community?  What’s interesting about this hypothetical is, even though it would put the remaining EDA companies in a position to take advantage of this opportunity they might not be able to.

Ed:  Just to play devil’s advocate, why wouldn’t that next set of players, whoever they are, be able to take advantage of the sudden disappearance of the big three?    And who do you consider to be that next set of players?

Tom:  Good questions.   But let me respond by saying what they will need to provide.

So, the next big three will have products that have great user interfaces, provide online collaboration, and be part of a new ecosystem that enables innovation.  The industry already has advanced technology but needs graphical and command-line interfaces that exploit the online design environment.

Second, designers don’t necessarily sit in the same building but often have to work on the same problem. For example, two or more designers should be able to share the timing database and bring up the same timing path without having to rerun static timing analysis and do it within minutes no matter where they are in the world.

Finally, the current EDA ecosystem is in the dark ages, there needs to be a new model that facilitates new algorithm and tool development with a reward system.

Ed:  Tom, thanks again for your insights.

 

Three Shifts for SIP

Tuesday, March 22nd, 2011

Ken Brock is the Product Marketing Manager for DesignWare Logic Libraries at Synopsys.  Ken shared with us here his view of the trends he sees for the future of semiconductor IP.

 

What Does the Future Hold for Semiconductor IP?

The marketplace for semiconductor IP (SIP) continues to grow at double digit rates. According to Gartner Dataquest, the number of third-party semiconductor design IP blocks in an average chip design will double from the current level and the SIP market will reach $2.3B in 2014. IBS and Semico believe the SIP market will be greater than $3 billion in 2014.

We see six major trends in IP:

  • Convergence: The increased demand for “Smart” consumer electronics is driving more features and functionality into a single device such as the latest craze in tablets shown at this year’s Consumer Electronics Show (CES). This trend is causing significant changes in SoC designs in areas such as power and performance requirements that drive technology node migrations, and in increased clock frequencies to keep up with bandwidth needs.
  • Core versus Context: Does this function differentiate the SoC? Interfaces like PCI Express® and USB have to work but they don’t generally differentiate the SoC.  As an IP vendor, we see many different applications spaces for our IP and we have to ensure that IP works over a broad range of configurations and products.
  • Fab-outsourcing: More outsourcing of manufacturing means more opportunity for customers to use off-the-shelf IP to meet their design requirements, and more demand for IP vendors to create high-quality IP on the most advanced process nodes.
  • Power, Performance, Area: As many semiconductor designs compete for the key sockets, having the fastest performance, lowest power and smallest area is often a key differentiator of the design with respect to processor performance, battery life, packaging cost and silicon cost. Choices of foundation IP (memory and logic) providers make a big difference between winners and also-rans.
  • Consumer-driven schedules: Shorter time-to-market and more features means that designers need to de-risk schedules by using high-quality IP solutions that have been proven time and time again in the market place.
  • Expense control: It is often less expensive for companies to buy third-party IP than to develop it themselves. This is particularly true in advanced nodes where the complexity of IP development increases rapidly with increasing data rates, restricted design rules and increasing variability. As an example, our estimate is that a 28nm standard cell and memory IP platform is at least five to 10 times as complex to design and verify as compared to a similar platform at 40nm.

With these trends as the backdrop, we see significant shifts in the SIP market as it continues to evolve during the next five years:

  • Most SoCs will have about 70 to 80 percent of their functionality in reused IP (internal and/or 3rd party). The majority of these IP blocks will be memories with thousands of instances per chip all connected with a variety of standard cell configurations. Optimized standard cells and memories can significantly impact the performance, power and area of a SoC.
  • Individual IP products will yield to more complex IP subsystems. These subsystems will include application-specific blocks and software. IP integration services will become increasingly important to validate the IP in the system context.
  • Multi-core designs will drive increasingly complex architectures. A virtual prototype of the IP and the larger SoC will enable earlier and more efficient development of application software and middleware.

This is a pivotal time for the semiconductor IP industry as companies strive to develop the best solutions to help designers accelerate their time from concept to implementation. These solutions generate value throughout the design chain by accelerating hardware/software integration and systems validation, allowing efficient SoC architecture exploration and optimization, creating and optimizing functional blocks, and using high-quality semiconductor IP. Designers are turning to trusted third-party SIP solutions to help integrate advanced functionality with the least amount of risk. Winners will choose wisely.

 

Chip Killers: keeping design managers awake

Monday, February 7th, 2011

Am I gonna make tapeout in time?Liz and I attended a panel at DesignCon that asked the question: what are you doing about the chip killers that delay your tapeout? That’s an intriguing, possibly unanswerable thought, since we’ve asked that question virtually since EDA’s inception. Ed Sperling of Systems-Level Design moderated the panel which had on it: Sunil Malkani of Broadcom, Ravi Damaraju of Juniper, Ramon Macias of NetLogic, John Busco of NVIDIA and Bernard Murphy of Atrenta.

Sperling moderated a lively discussion; questions that he or the panelists or audience posed highlighted the ongoing nature, or unanswerability of the topic. Some were:

• As designers and design managers, what keeps you up at night?

• If your design has to finish in half the time that your previous project took, do you start with a [design methodology and flow] clean slate?

• How do you get hardware and software engineers to work together?

• What’s good enough to get the design out the door?

• How do you define failure?

• What’s the price of failure?

• Who owns quality?

• What do you do when your next project is 4X the size of your last design? Throw people at it? Make the tools do more? Run faster? How?

• How do I turn around a design in a month and get all of these [now-required] apps on it?

• Why does place & route have to be flat?

• When will P&R, timing analysis have to break down the design hierarchically?

• How can verification be improved so that its pessimistic estimates won’t require designers to over-design?

The panelists all bemoaned the dueling standards that plague EDA, attributing them to companies wanting to gain marketing advantage, to the detriment of EDA users.

Sperling will publish a transcript of this panel in a future issue of System-Level Design. Nic Mokhoff published a summary of the panel the next day.

Finally, I have a question: why does DesignCon schedule a management-level panel on a day when the exhibit floor isn’t open? Doesn’t help DesignCon panels’ attendance, which has been paltry for years, seems to me.

– end –

Who owns IP quality?

Monday, January 31st, 2011

Piyush Sancheti of Atrenta brings up a good point: for Ip to work as we envision it can, what players have to contribute to the quality effort? And what does each player type need to contribute? http://bit.ly/gpAHI1

Can timing constraints disasters be averted?

Friday, January 14th, 2011

ron-craig_for-edblog

Ron Craig, Senior Marketing Manager at Atrenta and an expert on the subject of timing constraints, was good enough to sit down with me (Liz Massingill) recently to talk about the subject—what the current problems are and how to fix them. This is the result of my interview with Ron.

Liz: Ron, I was shocked to see, in the survey you conducted, that 94% of designers have timing constraint problems that could stop their current designs dead in their tracks.  But they also don’t see a way to change their current methodology.  WHY?!?!?!?!

Ron: There’s certainly no doubt that timing constraints remain and will continue to be a problem for design teams. The irony is that even though timing constraints are repeatedly an issue, most of these design teams feel that they know how to address all the problems that typically arise. It’s almost that the problems are viewed as less severe if the solutions are known.

Liz: Seems like the problem is more about changing the mindset. But why are designers running into increasing clock domain issues in the first place? Use of more IP?   Process nodes going down to the next level?   More complex designs?

Ron: The key culprit here seems to be IP. With IP, the functionality is reusable but the timing constraints are often not. Third party IP developers may well be experts in what the IP is supposed to do but not necessarily its implementation, leaving design teams with incomplete and inadequate timing constraints. On the other hand, IP reused from another design may well have been constrained in a way that’s not compatible with how you want to use it in your chip – especially if you need to change how the IP behaves. In today’s designs where IP amounts to 70% or more of a typical SoC, you end up with the constraint-driven implementation process becoming increasingly risky.

The process shrinks and more complex designs mean you simply can’t get away with having inadequate timing constraints anymore.

Liz: Well, what can they, ­or more appropriately, their project managers or internal CAD departments do about this increasing problem?

Ron: The key is to introduce more certainty into the whole process. Rather than taking an optimistic, or reactive approach to timing constraints, it makes a great deal of sense to put some effort in up-front to make sure that they are good. Many of our customers have noted that they simply can’t deal with the number of iterations it takes to refine timing constraints during the implementation phase of their projects, so they’re working on finalizing them up front as part of their RTL handoff. The trick for project managers or CAD people will be to introduce a methodology that their front end teams (who aren’t necessarily timing constraint experts) can easily adopt, and this is where comprehensive automated solutions such as SpyGlass-Constraints come into play.

Liz: So why isn’t this happening? Seems to me that an ounce of prevention is worth a pound of cure, as they say.

Ron: Let’s look at the two camps. First of all you have the RTL or front end team, who historically don’t want to take ownership of any part of the implementation process (even they know the design well enough to define its constraints). On the other side of that handoff ‘wall’ you have the back end team who feel that their expertise in this area, coupled with whatever the implementation and timing tools complain about, is enough of a solution. So depending on which side of that wall you sit on, you may feel that it’s either not your problem….or not a problem at all.

Liz: But we know there IS a problem, and it’ll only increase. So where in the design flow should project managers look first for a fix?

Ron: There is often a perception that timing constraints can’t be fully defined until you are actually using them – until you are in the thick of implementation or timing analysis. The problem with this is that your constraints end up being written so that you can close timing, instead of being defined to set the ground rules for timing closure. A classic example of this is the definition of timing exceptions – they’re often defined to mask timing violations, but in most cases they’re not exhaustively verified. A timing exception is a design characteristic, so can be defined and proven up-front before the implementation process even starts. It’s like an architect finalizing the plans after the building is complete. If your objectives aren’t clear how do you know when you are done?

Liz: I see what you are saying—it’s like putting the cart before the horse. Stop me, Ron, if I use another one of these old sayings. I’m dating myself. So who’s out there with technology that can help change the methodology and fix the timing disaster that’s looming?

Ron: It’s been possible to do some rudimentary timing constraint analysis in a range of implementation and STA tools since the advent of timing driven optimization. The problem with this approach, however, is that it’s largely a reactive one, and as a result doesn’t help reduce the risks in your implementation process. More recently, vendors (often ones outside the implementation/STA space) have started to provide solutions that allow the user to check the correctness of their constraints before implementation. What we’ve done with SpyGlass-Constraints is to take it one step further and look how timing constraint analysis is part of the bigger picture of reducing implementation risk. A great example of this is how we use our constraint verification methodology to ensure that data such as clock setup is in good shape before you use it to drive clock domain crossing (CDC) analysis. Again, it’s all about finding the issues up front and reducing risk later.

Liz: Well it’s intriguing…a Titanic-like iceberg of a design problem out there and we’re forging ahead…like the Titanic?

Ron: (laughs) Indeed – though given that the Titanic was built in my home city I always feel the need to point out that this particular disaster came about as a result of pilot error! To take your analogy further, I guess that the ‘iceberg’ here is a failure to close timing. Better guidance will definitely help you avoid that one.

Liz: Who knew? (laughs) Well, where can we learn more about this problem and how to fix it? Oh…and your customer survey…can we get a look at that? Sounds like some compelling information in there.

Ron: Yes, the customer survey was VERY telling and gives us a good leg up on what designers need to close at RTL for the next several generations of designs. In its current form, because we talked to customers, we can’t release it.

However,  Bernard Murphy WILL refer to it at length in his DesignCon panel.

Liz: What panel is that?

Ron: At DesignCon we will be holding a panel on: “The Same Chip Killers keep Delaying your Schedules – What are you doing about it?” moderated by Ed Sperling, editor of System-Level Design. The panelists will discuss a broad range of issues, including timing constraints, the impact of IP etc. that repeatedly cause schedule slips. It will take place on Monday, January 31 at 4:45 p.m.

Liz: Sounds like a crucial discussion.   I’ll be sure to attend!

Gianfagna on EDA and IP merging, annexing of embedded software

Monday, July 12th, 2010

mikeg2The pre-DAC acquisitions of Denali and Virage drastically realign the core of the EDA industry. When IP first came on the scene here in the US, (I think 3Soft was the first IP company I saw), many people figured that IP would become another form of delivery for chip designs – and that they would come from the semiconductor companies.

The EDA executives’ explicit remarks about how IP is key to their continued growth could turn EDA into an industry of IP haves and IP have nots.

How does this EDA realignment affect customers? We asked Atrenta vice president of marketing and industry voice Mike Gianfagna, ” What does the EDA industry realignment mean for customers?”

Here’s what he said:

Realignment can mean two things that are related, but a bit different.

One form of realignment we’re seeing is the IP market merging into the EDA market. This is definitely good for IP customers. Effective IP reuse requires a blend of quality, highly validated IP and a good reuse methodology. The methodology need is for both authoring IP to be reusable and implementing the reuse itself. EDA is a good place to bring all this together. Most larger EDA companies understand what it takes to deliver high quality, validated designs. They also understand what a reuse methodology should include. A lot of the smaller IP shops don’t have this perspective.

Another realignment is the “annexation” of embedded software into EDA. Synopsys is validating this trend with their buying spree, and Cadence is validating the trend with their EDA360 proposal and some buying, too. This is also good for the customer. If software development teams can help to drive the silicon creation process, we are going to see some new killer apps emerge as a result.
…………………………..
What do you think about the combination of IP and EDA? Let us know in the “comments” section.

– end –

On Synopsys buying Virage

Saturday, June 12th, 2010

We asked three EDA figures to comment on how the Synopsys purchase of Virage would impact the EDA and IP industries. Here’s what they said.

…………………………………………………………………………………………………..

mike-gianfagna534c2x3x3008This acquisition puts Synopsys squarely in the front of the pack as far as IP suppliers go. This trend could be quite significant. Successful IP reuse is a combination of the right EDA tools, best practices methodology and well-designed IP. The EDA vendor is a pretty good place for all that to come together. ARM remains the exception to this rule, and several other rules for that matter.

Mike Gianfagna
Vice President, Marketing
Atrenta, Inc.

…………………………………………………………………………………………………………….

hogan1I don’t see how this doesn’t make Synopsys a competitor with ARM on physical IP and ARC processor. ARM should start feeling like it is getting surrounded by Synopsys.

Jim Hogan
EDA investor

………………………………………………………………………………………………………….

cobyzelnik2With EDA trying to expand its scope and grow beyond its traditional boundaries (see EDA360), and with small and medium size IP vendors struggling to grow, basic economy forces are pushing this trend.

Synopsys has already been a formidable IP player and Cadence now entered it with its recent acquisition of Denali.

There are still plenty of smaller IP players so we’ll see further consolidation playing out. The IP segment has been trying to define and position itself between EDA and semiconductors. We all wondered if IP would become an intrinsic part of the semiconductor industry, the EDA industry, or stand on its own. These days we clearly see that the IP pendulum has shifted toward EDA.

The outlier is of course ARM which is a different beast, in some ways closer to semiconductors: i.e., look at how ARM competes with Intel. With a market cap equivalent to Synopsys and Cadence put together, ARM is simply too big for that.

Coby Zelnik
CEO
Sagantec

– end –

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