Posts Tagged ‘SystemVerilog’
Thursday, October 26th, 2017
Dr. Philippe Faes and Dr. Hendrick Eeckhaut together founded Sigasi in 2008. Since that time, Belgium-based Sigasi has accomplished the impossible: Taking the best elements of software design and applying them to hardware design. The Sigasi Studio IDE takes the type of feature-rich development environment that facilitates software design and redefines it for hardware design.
Early one morning last week, I spoke by phone with Hendrick Eekhaut, who serves as CTO at Sigasi. He was in Belgium, I was in California. After our conversation, he headed out to dinner; I headed in for breakfast.
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Tags: DAC, DVCon, Eclipse, EDA, Emacs, ESD Alliance, Ghent, Hardware design, Hendrik Eeckhaut, Philippe Faes, Sigasi, Sigasi Studio, SystemVerilog, Verilog, VHDL
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Wednesday, August 28th, 2013
Perfectly suited by nature to teaching, when affable Cliff Cummings steps up to conduct his Verilog course, the class is in for a treat. From the get-go, Cliff establishes a tone of respect, humor, and openness to questions of any kind. He encourages students to interrupt when they don’t understand, to stand up, sit down, resort to coffee and/or carbs, and in all ways to relax and enjoy the learning experience.
There’s something additional, however, that Cliff brings to his inspired task of teaching and that’s his decades of involvement with the Verilog language, its evolution, standards, and implementation. What Cliff Cummings doesn’t know about Verilog and SystemVerilog, isn’t worth knowing. Period.
This week, Cliff is teaching Verilog-2001 Design & Best Coding Practices in Silicon Valley – specifically, in the offices of EDA Direct – and I’ve been lucky enough to attend. Not being a Verilog expert, I approached the class with some trepidation, but found to my delight that I was not the only one among the 8 engineers in the room “new” to the language. We’re all engineers, but we’re not all Verilog designers and hence it’s a class perfectly suited to our skills, interests, and goals.
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Tags: Cliff Cummings, EDA Direct, IEEE Verilog standard 1364, OVM, Qualis, Stuart Sutherland, Sunburst Design, SystemVerilog, Tektronix, UVM, Verilog-2001, VHDL
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Thursday, February 21st, 2013
If you’re in EDA and haven’t heard of Verific Design Automation, it would appear you haven’t been listening. Michiel Ligthart, Verific President and COO, told me in a recent phone call that few people in the industry are unaware of his company’s offerings: “We’re very well known in the industry. Everybody who works in EDA knows us, or if they don’t, we are no more than 2 or 3 phone calls away.
“Verific is a little bit different kind of company. We are a small solutions providers, but we do not have an end-user product. Instead, we provide SystemVerilog and VHDL parsers that we license to EDA companies, and to semiconductor companies that build EDA products for internal use or for their customers.”
I asked why such companies don’t build their own parsers, and he said, “In fact, they could. These are based on IEEE standards and anyone could build them, but the parsers must be the same for everyone. If you can buy them from somebody else, rather than build them, it means you can concentrate on your distinctive solutions. Verilog parsers from companies like Cadence or Synopsys all have to adhere to the same standard.”
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Tags: Abhijit Chakrabarty, Michiel Ligthart, parsers, Rob Dekker, SystemVerilog, Verific Design Automation, VHDL
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Wednesday, February 6th, 2013
Now in its 25th year, DVCon is coming up in a couple of weeks in Silicon Valley. In terms of process nodes, 25 years is about twelve generations. In terms of dog years, it’s about four generations. In terms of the life of Stan Krolikoski, however, 25 years is only part of one career. It’s also the amount of time Stan’s been going to DVCon, even though it had a different name when he attended the first such conference back in 1988.
When I spoke with Stan by phone earlier this week, I asked if he’s been to every single conference since then. He laughed and said, “Absolutely! Looking back to 1988 – despite all of the mergers, and the coming together of various conferences, and the end of the HDL wars – I’ve been to every one of them!”
There’s nobody else who’s been to them all? Stan laughed again, “I don’t think so. They’ve either retired, or left the industry. Although I do think Dennis Brophy has been coming for a long time, but probably not all the way back to the beginning.”
Where was the first conference held in 1988? Stan said, “It was in Newport Beach. Why? Who knows. Back in the day, a number of meetings were held in Newport Beach. Maybe it was a destination, or maybe it was because there were a lot of defense contractors in the area. Remember that VHDL-87 had just come out and the language had a connection to the Department of Defense.”
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Tags: Accellera Systems Initiative, DVCon, Graham Bell, HDL, HDLCon, IVC/VIUF, JL Gray, Karen Bartelson, Stan Krolikoski, SystemC, SystemVerilog, UPF, UVM, Verilog, VHDL, Wally Rhines
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Thursday, March 15th, 2012
If you missed this week’s Blue Pearl Software workshop in Silicon Valley, you’re in luck – they’re holding it again on April 19th.
These workshops offer not only the opportunity to learn about Blue Pearl’s technologies, they’ll also let you brush up on your acronyms – FPGA, ASIC, SOC, CDC, SDC, SV, VHDL, and RTL – though not necessarily in that order.
Blue Pearl sells a suite of tools offering “comprehensive RTL analysis, clock-domain crossing [CDC] checks, and automated Synopsys Design Constraints [SDC] generation for FPGA, ASIC, and SOC designs.”
Release 6.0 was announced in February at DVCon 2012, where I spoke with Shakeel Jeeawoody, Director of Product Marketing at Blue Pearl.
Jeeawoody said, “We provide tools for linting, clock-domain crossing, and automated SDC generation – things people use to constrain their synthesis. Here in Release 6.0, a major new feature includes language coverage. (more…)
Tags: Altera, ASIC, Blue Pearl Software, CDC, clock-domain crossing, FPGA, RTL, RTL analysis, SDC, Shakeel Jeeawoody, SOC, Synopsys, Synopsys Design Constraints, SystemVerilog, Verific, Verilog, VHDL
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Friday, February 17th, 2012
Here’s your February Pop Quiz.
******************
1 – DVCon 2012 starts on February 27th. The conference was first held in _____.
a) 1989
b) 1995
c) 1998
d) 2003
2 – The IEEE Standards Association [IEEE-SA] oversees approximately _____ standards and _____ standards under development.
a) 500, 900
b) 800, 600
c) 900, 500
d) 700, 900
3 – The IEEE Standard associated with VHDL is _____.
a) IEEE Std 1064
b) IEEE Std 1076
c) IEEE Std 1164
d) IEEE Std 1176
4 – Accellera merged with _____ in 2011.
a) VSIA
b) OSCI
c) OCP-IP
d) OVI
5 – DVCon is managed by MP Associates, the same group that manages _____.
a) ICCAD
b) DesignCon
c) Semicon
d) ISQED
6 – The 2007 General Chair of DVCon was _____.
a) Tom Fitzpatrick
b) Stephen Bailey
c) Shankar Hemmady
d) Gabe Moretti
7 – SystemVerilog was donated to Accellera in _____.
a) 2000
b) 2001
c) 2002
d) 2003
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Tags: Aart de Geus, Accellera, Andrew Piziali, Brett Cline, Brian Bailey, Cadence, Cliff Cummings, CPF, DVCon, Gabe Moretti, Gary Smith, Grant Martin, IEEE Standards, JL Gray, John Cooley, Karen Bartleson, Kathryn Kranen, Magma, Mentor, MP Associates, OSCI, OVI, OVM, Paul McLellan, Rajeev Madhavan, Richard Goering, Synopsys, SystemC, SystemVerilog, Ted Vucurevich, UPF, UVM, Verilab, Verilog, VHDL, VHDL International, Wally Rhines
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