Posts Tagged ‘Dusan Petranovic’
Thursday, March 24th, 2016
To speak with Herb Reiter about the rationale for multi-die packaging is a chance to follow a logical and energetic continuum from first principles to a final conclusion. Namely, that as the era of the ASIC subsides, the era of the multi-die package will arrive full force.
Reiter, President of eda 2 asic, will be reiterating this line of thinking, in conjunction with a panel of like-minded experts, at the upcoming EDPS conference in Monterey on April 21st. In anticipation of that session – “Multi-Die IC Design and Application” – we spoke by phone this week. The conversation was compelling.
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Tags: Asim Salim, autonomous driving, Cliff Hou, Dusan Petranovic, eda 2 asic, EDPS, Ford, Gary Smith, Google, Herb Reiter, ITRS, Ivor Barber, Multi-die packaging, Paul Silvestri, Riko Radojcic, TSMC 1 Comment »
Thursday, April 4th, 2013
Let’s be honest about this. The reason the Electronic Design Process Symposium takes place every year in Monterey is because of the surf and sunshine. Otherwise, this conference would be so much more appropriately located in Silicon Valley.
Oh well, where’s the harm? Just hop into your favorite woodie, be it a hybrid or an EV, don’t forget the suncream, sandtoys, and surfboard, and head on down to Monterey Bay for two days of great talks, good food, and quiet-ish contemplation, with an emphasis on -ish. The 20th annual EDPS awaits.
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Tags: Adapt-IP, Alcatel-Lucent, Aparna Dey, ARM, Brandon Wang, Cadence, Camille Kokosaki, Dan Nenni, Docea Power, Don MacMillen, Dusan Petranovic, E-System Design, eda2asic, EDPS 2013, Frank Schirrmeister, Gary Smith, Gene Jakubowski, Gene Matter, Gregory Wright, Guy Bois, Herb Reiter, Intel, Ivo Bolsens, James Colgan, John Heilein, John Swan, Kiron Pai, Luigi Capodieci GlobalFoundries, Mentor Graphics, Michael McNamara, Micron, Mike Black, Namraj Nandra, Naresh Sehgal, Net App, Nimbic, Oracle, Raymond Leune, Rob Aitken, SemiWiki, Space Codesign, Srinivas Nori, Srinivasa Banna, Synopsys, Tom Dillinger, Tom Quan, TSMC, Xilinx, Xuropa No Comments »
Thursday, March 29th, 2012
Here are the Top Ten reasons to be going to EDPS next week in Monterey:
10) Next week’s a lighter work week for most and the Monterey Peninsula is beautiful at any time of the year, but particularly in the spring.
9) The Electronic Design Process Symposium is in its 19th year, and everybody who’s anybody in EDA and its adjacencies has attended at one point or another.
Eight) The topics discussed at EDPS have always tracked the trajectory of the industry. In 2000, those topics included: deep sub-micron, distributed and web-based design methodologies, designer productivity, and maintaining modularity in an integrated design flow.
Here in 2012, technology evolution has driven a completely different set of topics: embedded processors, FPGAs, ESL, NUMA, EDA in the Cloud, Big Data and the Big Servers that serve them, low-power design, and 3d-ICs, among others.
7) Going to conferences is as much about conversations outside the sessions, as it is about presenting or listening within the sessions. EDPS is a boutique conference, where I promise you’ll have a chance for substantive conversations with the speakers, both inside and outside of the sessions.
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Tags: 3D-ICs, Altera, Arif Rahman, Azadeh Davoodi, Cadence, Deepak Sekar, Don MacMillen, Dusan Petranovic, EDPS, Electronic Design Process Symposium, Frank Schirrmeister, Gary Smith, Grant Martin, Hans Spanjaart, Herb Reiter, Ian Ferguson, James Colgan, Jim Hogan, Kiron Pai, Marc Greenberg, Mentor, Mike Hutton, Monterey Peninsula, Naresh Sehgal, Phil Marcoux, Qi Wang, Riko Radojcic, Samta Bansal, Sandeep Goel, Sangeeta Aggrwal, Sri Ganta, Steve Leibson, Steve Smith, Steven Pateras, Synopsys, Tom Spyrou 2 Comments »
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