Posts Tagged ‘Blue Pearl Software’
Thursday, September 21st, 2017
Silicon Valley based Blue Pearl Software is the quintessential EDA company: privately held, run by a seasoned team of EDA experts, and with a portfolio that includes tools for generating timing constraints, CDC analysis, both synchronous and asynchronous, RTL verification tools for methodology standards and design rules, and design management tools.
Similarly, Blue Pearl’s Ellis Smith is the quintessential CEO in EDA. Before founding his current company, Smith was CEO and President of Orora Design Technologies, CEO at TransEDA through that company’s IPO in 2000, and CEO at Exemplar Logic through its merger with Mentor Graphics in 1995. His experience also includes a stint as CEO at CrossCheck Technology, and years spent at Duet Technologies, CADAM, Versatec, Dictaphone, and 3M. Pretty much the whole history of the EDA industry in one CV.
It would be an excellent idea to sit down for a very long conversation with Ellis Smith to discuss his take on the history of this oh-so-interesting industry. Unfortunately, time was of the essence when I did get the chance to talk with him earlier this month, and the focus was principally on Blue Pearl.
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Tags: Altera, Blue Pearl Software, Cadence, ESD Alliance, Mentor, MicroSemi, Synopsys, Xilinx
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Thursday, June 20th, 2013
Great if you were able to attend DAC in Austin this month. Even better if you were able to attend the Monday afternoon Pavilion Panel on the how-and-why of networking for career growth. The topic may seem irrelevant to some of you, but networking sits as the center of successful career development and it’s definitely not for the faint of heart.
Sashi Obilisetty, Director, R&D at Synopsys, assembled a seasoned panel of experts to discuss the issue – How networking is crucial to professional growth – with the June 3rd panelist including Tufts University Professor and DAC 2014 General Chair, Dr. Soha Hassoun, Calibra Consulting President Jan Willis, and Blue Pearl Software VP Kavita Snyder. The panel discussion began with Jan Willis:
Jan Willis – I want to share three perspectives on the issue. First, networking matters a great deal – for changing jobs, for moving into other fields, and for changing your career trajectory. I didn’t realize how much it mattered until I found that 100-percent of my current business in consulting is a result of networking.
Second, sponsors are very different from mentors, not at all the same. Sponsors tap you on the shoulders and point out when a job is available that would be good for you going forward. Third, networking is critical and it’s important to spend time on it. LinkedIn is a wonderful thing, but it offers you a false sense of security that you have great connections. If you’re not working at networking, [your network] won’t work for you.
Soha Hassoun – I would like to emphasize that it’s important to network early on in your career. Some people wait until they are at the mid-point in their careers, but that is too late. Whether in academia or industry, it holds true – you need to start early.
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Tags: Blue Pearl Software, Cadence, Calibra Consulting, DAC 2013, Jan Willis, Kavita Snyder, Pavilion Panel, Penny Herscher, Sashi Obilisetty, Soha Hassoun, Synopsys, Tufts
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Thursday, March 15th, 2012
If you missed this week’s Blue Pearl Software workshop in Silicon Valley, you’re in luck – they’re holding it again on April 19th.
These workshops offer not only the opportunity to learn about Blue Pearl’s technologies, they’ll also let you brush up on your acronyms – FPGA, ASIC, SOC, CDC, SDC, SV, VHDL, and RTL – though not necessarily in that order.
Blue Pearl sells a suite of tools offering “comprehensive RTL analysis, clock-domain crossing [CDC] checks, and automated Synopsys Design Constraints [SDC] generation for FPGA, ASIC, and SOC designs.”
Release 6.0 was announced in February at DVCon 2012, where I spoke with Shakeel Jeeawoody, Director of Product Marketing at Blue Pearl.
Jeeawoody said, “We provide tools for linting, clock-domain crossing, and automated SDC generation – things people use to constrain their synthesis. Here in Release 6.0, a major new feature includes language coverage. (more…)
Tags: Altera, ASIC, Blue Pearl Software, CDC, clock-domain crossing, FPGA, RTL, RTL analysis, SDC, Shakeel Jeeawoody, SOC, Synopsys, Synopsys Design Constraints, SystemVerilog, Verific, Verilog, VHDL
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