Posts Tagged ‘Accellera’
Thursday, October 12th, 2017
DVCon Europe 2017 will be in Munich next week, a great destination for tourists and technologists alike. This is the fourth year the conference will occur in Europe, the original Silicon Valley based version now in its 27th year.
DVCon Europe General Chair Oliver Bell and I spoke this week by phone about the upcoming event; he was in Germany and I was in Northern California. I offered that Munich is a beautiful city, and he agreed.
“The conference will be in downtown Munich,” Bell said, “at the Holiday Inn. This is a really nice hotel, located near to Marienplaz, and easily reachable from public transportation.”
Bell then laughed and acknowledged that, as famous as the city’s Oktoberfest may be, it’s better that DVCon is being held several weeks after that particular annual exuberance has run its course. The city’s just that much more calm and enjoyable, he noted, after the hundreds of thousands of Oktoberfest revelers have returned to their normal pursuits.
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Tags: 2017 DVCon Europe, Accellera, ARM, Audi, Berthold Hellenthal, Bosch Sensortec, Cadence, Horst Symanzik, Infineon, Intel, Martin Barnasconi, Mentor Graphics, Munich, Nokia, Oliver Bell, Rohde & Schwarz, STMicro, Synopsys, SystemC Evolution Day, Technical University of Munich, UVM
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Thursday, September 14th, 2017
Prakash Narain is a long-standing member of the EDA community, having helped found Real Intent in 1999. In August 2016, I interviewed Dr. Narain at length about the technology at the core of the company. This week we spoke again, starting with an update of the company’s announcements around DAC in June, which involve further advancements in clock-domain crossing analysis and sign-off.
Real Intent must be doing something right, because Narain seems as enthused about the prospects for his company as someone who has just launched a tech start-up. It takes stamina and courage to sustain that optimism, and market success. Narain says his organization has both.
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Tags: Accellera, ESD Alliance, IEEE, Prakash Narain, Real Intent
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Thursday, February 23rd, 2017
Accellera has just announced that Lu Dai, Senior Director of Engineering at Qualcomm, is the new chair of the organization.
Although Intel’s Shishpal Rawat, recently retired from Intel, is a hard act to follow as Accellera Chair given his long, productive years leading the organization, if anyone can do it Lu Dai can. He’s enthusiastic, energetic, optimistic, and an engineer – and not necessarily in that order.
Before talking about Accellera in our phone call this week, Dai spoke about DVCon, anchor tenant of Accellera’s outreach to design and verification engineers around the world. This next week, the Silicon Valley version will unfold in San Jose, with DVCon India happening in September, DVCon Europe in October, and the first-ever DVCon China in April.
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Tags: Accellera, DVCon, DVCon China, DVCon Europe, DVCon India, DVCon U.S., Lu Dai, Qualcomm, Shishpal Rawat
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Thursday, February 2nd, 2017
If you’re going to chair a conference, according to DVCon 2017 General Chair Dennis Brophy, don’t do any work. Instead just delegate, because if you’ve done that properly, the committees will craft a great program and a great gathering.
Hence, per Brophy, this year’s DVCon is going to be great. He’s done nothing, the committees have done everything, and their work has been inspired.
You must bring something to the effort, I insisted.
Brophy chuckled and deflected my question: “I’ll defer to Wally Rhines’ thesis: The learning curve definitely doesn’t stop, even though Moore’s Law is slowing. And there will be a lot of opportunity to learn this year at DVCon.
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Tags: Accellera, Dennis Brophy, DVCon 2017, IEEE 1800.2, SystemC, UVM
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Thursday, December 8th, 2016
For the first time ever, a citizen of the EDA Nation will be President of the IEEE, with 400,000+ members, the largest professional organization in the world. Karen Bartleson is serving as IEEE President-Elect here in 2016, and will serve as IEEE President starting in January 2017.
Prior to her current role at IEEE, she was President for two years of the IEEE Standards Association, a group with total membership exceeding 17,000. And prior to her leadership there, as every citizen of the EDA Nation knows, Bartleson honed her myriad skills through 20 years of distinguished service at Synopsys.
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Tags: Accellera, Cal Poly San Luis Obispo, IEEE, IEEE Standard 1801-2009, IEEE Standards Association, Karen Bartleson, Si2, UPF
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Thursday, July 14th, 2016
Intel’s Shishpal Rawat has been Chair of Accellera for 6 years and is currently serving as President of CEDA, IEEE’s Council on Electronic Design Automation. In previous discussions, Rawat has insisted that his leadership is not what makes these organizations work. Only the enthusiastic efforts of the many members guarantee that both Accellera and CEDA continue to shape ideas, standards, and forward progress within design automation and its adjacent technologies.
Two years ago, I enjoyed a lengthy interview with Rawat about all of this, described here. This year, I’ve chatted with Rawat at DVCon in San Jose in March, and again by phone just prior to DAC in June. During the phone call, Rawat focused on CEDA’s activities at DAC in Austin. He told me the upcoming Sunday night panel, set to be moderated by SRC’s Bill Joyner on June 5th, was a new and very exciting addition to the DAC program.
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Tags: Accellera, CEDA, Council on Electronic Design Automation, DAC, DAC Young Faculty Workshop, DATE, Design Automation Conference, DVCon, ICCAD, IEEE
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Thursday, May 26th, 2016
Ten years ago, Rich Weber and Jamsheed Agahi surveyed an industry they knew well – they each had 10+ years’ involvement in the technology – and found no one was providing hardware/software interface solutions. So in February 2006, they founded a company to “provide good solutions to the industry” and got busy coding. They had their software up and running by DAC, held that year in San Francisco, were featured in the July 2006 issue of EETimes, and were working with their first customers by the end of the year.
Those early successes were an indication of the credibility of Semifore Inc. and a reflection of the singular vision of founders who knew each other well; they had worked with together at various companies prior to 2006, Data General, Silicon Graphics, StratumOne and Cisco Systems. Starting Semifore together was the logical next step in their collaborations. Now ten years on, both founders are still with the company
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Tags: Accellera, CoStar Design Director Platform, Design Automation Conference, Heart of Technology, IP-XACT, Jamsheed Agahi, Rich Weber, Semifore Inc., SPIRIT Consortium, SystemRDL, UVM
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Thursday, March 17th, 2016
Mentor Graphics’ Tom Fitzpatrick gave a lunchtime talk at DVCon several weeks ago summarizing recent efforts to build a standard [set of standards?] around portable stimulus for verification. The room was packed with over 200 people and his talk was sufficiently complete, nobody asked any questions.
After his presentation, however, I did hear some comments. Namely that these types of standards are quite complex and difficult to develop. Hence, setting an actual delivery date of January 2017 for Portable Stimulus Standard Version 1 [PSS V1] is quite aggressive and optimistic.
I was not fully informed about Accellera’s Portable Stimulus Working Group [PSWG] prior to Fitzpatrick’s talk, so could not judge whether January 2017 is or is not overly optimistic as a delivery date for the standard. Since DVCon, I have studied the slides and attempted to better understand what this is all about: What is a Portable stimulus and what would a set of standards look like?
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Tags: Accellera, Accellera PSWG, Agnisys, AMD, AMIQ EDA, Analog Devices, Breker Verification Systems, Cadence, Cisco, DVCon, Faris Khundakjie, IBM, Intel, Mentor Graphics, NVIDIA, NXP, Portable Stimulus Working Group, Qualcomm, Semifore, Synopsys, Tom Anderson, Tom Fitzpatrick, Vayavya Labs
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Thursday, February 4th, 2016
On a phone call last week with the DVCon 2016 General Chair, Synopsys’ Yatin Trivedi, and 2016 Technical Program Chair, eInfochips’ Ambar Sarkar, I was again reminded of two unalienable truths: DVCon is a labor of love for those who have been involved for so long, and without these people the conference simply would not exist.
DVCon is the granddaddy of all design and verification conferences. It’s been housed annually in Silicon Valley since before the beginning of time, this year from February 29 to March 3 at the DoubleTree Hotel. As inevitable a part of the yearly conference cycle as DVCon may be, however, always remember that nothing is forever.
Learning and networking opportunities like DVCon only exist because a group of over-achieving volunteers continue to infuse the event with their special brand of energy and credibility. The conference goes on and on, because of the selfless dedication of the folks who carve time out of their busy professional lives to lead it — to solicit, vet and assemble the technical program, and to solicit, vet and assemble the exhibition hall (a unique ‘science fair’ sort of a deal that opens every afternoon after the technical sessions have wrapped up for the day).
But these kinds of volunteers do not always step forward and even when they do contribute at this level, their efforts often go unnoticed. Hence, when you think of DVCon, remember to be grateful to the team that brings it to you. Nothing lasts forever, even if DVCon seems likes it could. End of sermon.
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Tags: Accellera, Ambar Sarkar, Dennis Brophy, DVCon 2016, DVCon Europe, DVCon India, Lynn Bannister-Garibaldi, Shishpal Rawat, SystemC Users Group, Yatin Trivedi
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Thursday, September 25th, 2014
Last week I had a chance to chat by phone with Accellera Chair Shishpal Rawat, and when I say chance that’s accurate. Rawat is so busy these days, it’s hard to believe he has time for any extraneous conversations. Not only does he have a full-time job at Intel, he has been chair of Accellera for four years and now is ramping up to take over the reins at CEDA at well.
Among other activities, both Accellera and CEDA sponsor several key conferences in the industry. Accellera is the primary sponsor of the Design and Verification Conference and Exhibition (DVCon). I asked Shishpal about this year’s efforts to take DVCon on the road and how that dovetails with the changes he’s seen at Accellera over his years of leadership.
He said, “Without a doubt, the biggest change is the international outreach that we are now doing in our programs. DVCon will debut in Bangalore this month and will debut in Europe next month on October 14th and 15th in Munich. Expanding the conference this way has required a great deal of work on the part of local dedicated volunteers in both India and Europe, in addition to the efforts of our established corps of hardworking people. We expect a very big group of attendees at both of these shows, which adds to the work load for everyone involved.”
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Tags: Accellera, Cadence, CEDA, Dennis Brophy, DVCon, IEEE Standards, Intel, Jill Jacobs, Karen Pieper, Mentor Graphics, Shishpal Rawat, Synopsys, System Verilog AMS standard, SystemC, UPF, UVM, Verilog
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