Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
Intel’s Shishpal Rawat: Multiple hats, Singular focus
September 25th, 2014 by Peggy Aycinena
Among other activities, both Accellera and CEDA sponsor several key conferences in the industry. Accellera is the primary sponsor of the Design and Verification Conference and Exhibition (DVCon). I asked Shishpal about this year’s efforts to take DVCon on the road and how that dovetails with the changes he’s seen at Accellera over his years of leadership.
He said, “Without a doubt, the biggest change is the international outreach that we are now doing in our programs. DVCon will debut in Bangalore this month and will debut in Europe next month on October 14th and 15th in Munich. Expanding the conference this way has required a great deal of work on the part of local dedicated volunteers in both India and Europe, in addition to the efforts of our established corps of hardworking people. We expect a very big group of attendees at both of these shows, which adds to the work load for everyone involved.”
I asked Shishpal how Accellera will know if all of this effort has been worthwhile and if the group should continue to take DVCon on the road.
Shishpal answered easily, “We will ask our member companies. They are the ones most likely to participate in these activities in large numbers. Plus, we’ll poll our EDA suppliers and get their feedback. ‘Has it been useful for their clients? What is the likelihood they will come again?
“Of course,” he added, “the cycle of topics offered at DVCon is an important draw. We also know that most companies cannot afford to send all of their employees to the conference, but perhaps the rest attend in the following years. If that’s the case, it may take more than just this year’s debut to find out if the conference has traction in India and Europe.”
What are some of the topics that are crucial to DVCon, I asked.
Shishpal said, “On the SystemC side, within Europe, Japan and Taiwan, the user group meetings have had good attendance for years. So we know this need will continue to be the core of DVCon.
“Of course, in Europe and India we will add activities around UVM, which is very popular, as well as UPF. So, there will be both SystemC and non-SystemC tracks in the program. This is what we sense the audience wants. From there on, it’s up to the technical committee to create a diverse set of program sessions that reflect evolution in the industry.”
As Accellera Chair, is Shishpal going to India and Europe for the DVCon ‘ribbon cuttings’ this fall?
He said, “Unfortunately, I can’t attend them all. Mentor Graphics’ Dennis Brophy, Vice Chair of Accellera, will represent Accellera in India, and I will be the representative in Europe in October.”
I asked Shishpal how he keeps up with his work and his volunteer activities as well.
He said, “There is a lot of activity going on for me over the course of every year, but Intel is very heavily involved in EDA standards. You will find Intel people have a presence in most of the subgroups of Accellera and Si2, so much so, that between the two organizations most of the standards are covered. And you can understand that from Intel’s point of view, my work with Accellera and CEDA contributes to that involvement.”
At my request, Shishpal clearly delineated between the work of the two organizations, CEDA and Accellera.
Shishpal said, “CEDA is devoted to industry professionals and looks at content and new techniques that will serve the EDA market, mostly within the academic domain. CEDA overlooks the content of DAC, DATE, ASP, and so forth, and works to get the right content for EDA and design development brought out into industry and commercialization.
“Accellera is performing standardization work for EDA tools and technology, standing at the boundary between where one tool finishes and the next operates. We have 13 working groups in Accellera, with Karen Pieper holding chair meetings regularly, so the standards being developed don’t conflict but work together. She is the one who keeps us all in line.
“Our current efforts are aimed at making EDA and IP standards widely available through the GET program that enables electronic download – both within Accellera and through the IEEE. The IEEE typically charges a fee for such downloads. However, some standards initially developed by Accellera have been donated to the IEEE with the intent of standardization and accreditation. We have made a special arrangement with the IEEE Standards Association to make the most popular standards available worldwide for free, whereby Accellera pays the IEEE a flat fee for downloads.”
Shishpal added, “After a standard is donated, the IEEE does a lot of work to get an international seal of approval for it. IEEE standards are worldwide standards, and this process is rigorous and expensive. It includes marshaling participation across many organizations, monitoring formats for the standards, being sure the standards meet certain metrics, and then organizing the vote to finalize acceptance. Once the IEEE standardization process is complete, IEEE hosts the standards on their site for user downloads.”
Changing direction, I asked Shishpal how he would characterize the applicability of Accellera’s efforts to the big bad world of third-party IP vendors.
“All IP developers, whether in-house or third-party vendors, are using established standards of SystemC, SystemVerilog, and so forth, which are the same standards used by component designers. In addition, they are using the IP-XACT standard, and the combination provides a single standard mechanism to guarantee compatibility amongst its users. Given that’s the case, it’s not surprising that companies like ARM, Intel, Texas Instruments, Sonics, Freescale, and NXP are members of Accellera.”
Given Rawat’s enthusiasm, I asked him to identify two or three major milestones he and others would like to be on the road map for the organization going forward.
He said, “We actually articulated those milestones quite clearly at DAC this past June in San Francisco. One is to finalize the verification standard UVM 1.2. We would also like to make that an international standard, via the IEEE, and have it accepted as an IEEE standard. Our working group is moving forward with that aggressively. We would like to get that process initiated by the end of 2014 and concluded by the end of 2015.”
He continued, “The next big thing that we would like to see is building the SystemVerilog AMS standard. Version 2.4 of Verilog AMS was released earlier this year, which was a great deal of hard work, and we would like to see the SystemVerilog version follow shortly.
“This is an important standard as it will address some of the fundamental differences between Verilog and SystemVerilog on how they treat some of the objects in analog design. We will need help from the user community to do that, but we are optimistic they will pitch in and help.
“Under the banner of the Design Technology Council, we successfully brought OpenAccess to life many years ago. We expect that same kind of success getting our SystemVerilog AMS standard into place. We need to look for experts and enthusiastic people willing to contribute time to figure this all out. And of course, it’s always a tussle between job and time allocated for this type of standards work.”
Speaking of the tussle, I asked Shishpal if all companies are as generous with their employees’ time as Intel seems to be when it comes to condoning participation in these types of standards efforts.
He said, “Influential leaders in the big companies understand the importance of this work. We have many Accellera companies who are heavily involved with standards drafting and coding standards such as UVM, UPF, etc.”
Are any companies so counter-intuitive in their thinking as to believe that pursuing standards actually reduces their ability to compete?
Answering philosophically, Shishpal replied: “Standards go through a natural cycle. If someone hasn’t actually tried to use them, they don’t work out. However, good standards are something that people are already using in practice.
“Verilog, for example, was initially a private language owned by Cadence. It went through phases of maturation after being made open, and eventually evolved into an important EDA standard. That is a very typical cycle. Plus, we don’t find people opposed to working on standards, because in truth these things actually improve the financial opportunities for the companies that embrace them.”
“In EDA, in particular,” Shishpal continued, “there is a lot of incentive to use standards. Previously, there were a lot of proprietary standards but over the years that has changed. GDS II became a de-facto standard, for example, and then the Liberty format came from Synopsys and became the de-facto standard.
“At this stage, we don’t see people trying to build their own standards in the workplace in EDA anymore. When you write a tool, there will be many stages in the life of that tool. Yes, there will be internal formats along the way as there is for any development cycle.
“But when you need to introduce that tool into the larger flow, you have to be able to exchange data between the various points in that flow. Standards sit at the boundary – they have to be done well, and they have to be definite. This is the only way to build a flow that will be useful and widely used by the customers.”
Shishpal added, “If you look at the interface between architecture and system-level development, there is a lot of need for innovation and eventually standardization. This is where a lot of work remains to be done. From a user’s point of view, however, even if there are setbacks along the way, standardization will be good for the industry. A great deal of effort is needed in this direction in the near future.”
Also on our phone call, PR Counsel Jill Jacobs added, “Standards always spawn innovation. And now, with IP being widely reused, standards are more important than ever.”
Closing out the conversation, I asked Shishpal how the heck he will be able to have the bandwidth to run both Accellera and CEDA.
He laughed and said, “Fortunately, there are volunteers in both organizations who are willing to help, and not only at the board level. From the working group chairs, to the promotions group chair, and on to the various committees, they are all putting in their time and I am happy to have them. Without their help, nothing would function!”
Tags: Accellera, Cadence, CEDA, Dennis Brophy, DVCon, IEEE Standards, Intel, Jill Jacobs, Karen Pieper, Mentor Graphics, Shishpal Rawat, Synopsys, System Verilog AMS standard, SystemC, UPF, UVM, Verilog