Archive for January, 2017
Thursday, January 26th, 2017
If you were to attend only one Kaufman Award dinner throughout your career, tonight’s might have been the right choice: a lovely meal in downtown Silicon Valley, and presentations full of warmth, respect, humor and clear-eyed admissions, all in honor of CMU’s Dr. Andrzej Strojwas, long-time CTO at PDF Solutions.
Having interviewed Prof. Strojwas some months ago when he was first named the 2016 Kaufman Award winner, and knowing the event was in the capable hands of the ESD Alliance, this evening’s ambiance was not a complete surprise. But the display of emotion and palpable affection with which Dr. Strojwas is held by colleagues and family was almost mesmerizing.
In fact, as PDF CEO John Kibarian hit his stride at the podium, detailing the lifetime of achievements and leadership at the core of Dr. Strojwas’ award commendation, there could be no looking away.
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Tags: 2016 Phil Kaufman Award, Aart de Geus, Andrzej Strojwas, Carnegie Mellon, ESD Alliance, IEEE CEDA, John Kibarian, Lip-bu Tan, Lucio Lanza, PDF Solutions, Shishpal Rawat, Steve Director, Wojciech Maly No Comments »
Thursday, January 26th, 2017
Next week, DesignCon 2017 will be underway at the Santa Clara Convention Center. As always, the program will include a lot of practical advice across a variety of design silos: Analog & mixed-signal modeling and design; modeling and analysis of interconnects.; PCB design, simulation, and fabrication; chip/package design and signal integrity considerations; EM interference; and various aspects of high-speed design.
DesignCon clearly continues to provide a learning venue for working engineers who deal with real-world problems, and again this year there will also be a lively exhibit hall.
Featured among the 185 exhibitors will be multiple companies offering tools for design – Cadence, Altium, Ansys, SiSoft, Mentor Graphics, Applied Simulation, EMA, DipTrace, Polar Instruments, SPISim, Valydate, XJTAG, and SpeedIC, among them.
Also exhibiting this year at DesignCon will be our own EDACafe.
Sanjay Gangal, President of IBSystems, and his team will be in Booth #1349 where they will be recording video interviews.
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Tags: Altium, Ansys, Applied Simulation, Cadence, DesignCon 2017, DipTrace, EDACafe.com, EMA, IBSystems, Mentor Graphics, Polar Instruments, Sanjay Gangal, SiSoft, SpeedIC, SPISim, Valydate, XJTAG No Comments »
Thursday, January 19th, 2017
Synopsys is undergoing a massive reset. Where not so long ago, it self-identified as the largest EDA company in the world, other words are now used to describe the enterprise: “Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing.”
As compelling as that description may be, some observers are questioning whether the marked differences between maintaining expertise in chip design, verification, IP, and IP integration versus maintaining expertise in software integrity are too wide to make for easy co-habitation under one corporate roof.
Some would say putting EDA and chip design together with software security is not a good recipe for the long-term success of the company. But are these critics correct?
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Tags: Cigital, Codiscope, Coverity, Forcheck, SNPS, Synopsys No Comments »
Thursday, January 12th, 2017
As we embrace a New Year, it is always a toss-up as to whether we are drawn to look to the past to understand our future, or to the future itself. The blank page. The untested waters. The mysterious frontier. Danger and opportunity seemingly mixed in equal proportions within the murky fog a-swirl in that not-so-crystal ball.
It’s within that spirit that I recalled this week a reverie that unfolded several years back while sailing the waters of Lake Gatun midst the Panama Canal. A reverie that attempted to synchronize the muscular optimism at the turn into the last century with the somewhat more tenuous outlook at the turn into this one.
That earlier reverie was tempered by remembering innovations such as the Vienna Secession, Futurism, Fin de siècle, Dada and Cubism – movements that propelled some observers from the nineteenth century into the twentieth – could hardly be said to reflect a stridently cheery outlook. Inversely, the angst and anxiety that oft-times characterize the narcissism of our own here-and-now – trends that have sometimes accompanied our complex journey from the twentieth century into the twenty-first – are profoundly repudiated by the engineering marvels that define this equally muscular New Age.
In truth, the past was never as rosy as we remember and rarely does the future fulfill our darkest premonitions. It’s simply the nature of the human comedy that we so thoroughly believe they do.
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Tags: Digital age, Eiffel Tower, Golden Gate Bridge, Panama Canal No Comments »
Thursday, January 12th, 2017
Are you building the IoT? Then you already know it’s a jungle out there.
Happily, the University of New Hampshire is offering an interesting service that should help. They’ll test your IoT device to see if it meets current Internet Protocal standards. Of course, understanding such a service presumes there are any standards in the first place – there are many, some very controversial – and also presumes you know how those standards are described within a veritable jungle of acronym-laden jargon.
But before we run through that rain forest of gobbledygook, let’s first review what the goals of the UNH InterOperability Lab are in establishing their IoT IP Testing Service. Those goals were laid out during an online press conference in December when the folks at the lab explained what they want to accomplish: Foster industry-wide collaboration, provide an extensive testbed for evaluating IoT devices, and train the engineers of tomorrow who want to help build the IoT.
These are clearly commendable goals, and the people behind the effort seem nothing if not cheerful and upbeat, but to fully understand what they’re doing you’ll first need to slog through the acronyms. Buckle your seat belt, it’s going to be a bumpy ride.
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Tags: IETF, Internet Engineering Steering Group, IOT IP Testing Service, IPv6, UNH-IOL, University of New Hampshire InterOperability Lab No Comments »
Thursday, January 5th, 2017
IEEE’s CEDA and the ESD Alliance – with help from their friends at PDF Solutions, Cadence, Mentor, Synopsys and ACM SIGDA – will host a dinner on Thursday, January 26th, in honor of the 2016 Phil Kaufman Award recipient: Dr. Andrzej Strojwas, Keithley Professor of ECE at Carnegie Mellon and long-time CTO at PDF Solutions.
Unfortunately, the last several Kaufman Award dinners were such over-the-top events – the 2014 event in honor of Dr. Lucio Lanza awash in glamour and luminaries, and the 2015 event in honor of Dr. Walden Rhines replete with zany zeitgeist and a roast from Intel-legend Craig Barrett unparalleled in the annals of EDA history.
The organizers of this year’s event may, therefore, find it impossible to craft something anywhere close to the previous two dinners, if the metrics of energy and frenetic glad-handing are the only ones of importance.
Of course, these are not the only two metrics of importance and nothing is ever impossible in EDA or IP, so do not despair.
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Tags: 2016 Phil Kaufman Award, ACM Sigda, Cadence, Carnegie Mellon University, Dr. Andrzej J. Strojwas, ESD Alliance, IEEE CEDA, Mentor Graphics, PDF Solutions, Synopsys 1 Comment »
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