Blue Pearl: Language Support & Workshops

If you missed this week’s Blue Pearl Software workshop in Silicon Valley, you’re in luck – they’re holding it again on April 19th.

These workshops offer not only the opportunity to learn about Blue Pearl’s technologies, they’ll also let you brush up on your acronyms – FPGA, ASIC, SOC, CDC, SDC, SV, VHDL, and RTL – though not necessarily in that order.

Blue Pearl sells a suite of tools offering “comprehensive RTL analysis, clock-domain crossing [CDC] checks, and automated Synopsys Design Constraints [SDC] generation for FPGA, ASIC, and SOC designs.”

Release 6.0 was announced in February at DVCon 2012, where I spoke with Shakeel Jeeawoody, Director of Product Marketing at Blue Pearl.

Jeeawoody said, “We provide tools for linting, clock-domain crossing, and automated SDC generation – things people use to constrain their synthesis. Here in Release 6.0, a major new feature includes language coverage.

“Previously we had partial coverage of VHDL and HDL, but we decided to use the Verific parser for the front end [announced in February], so now we have complete coverage of VHDL, SystemVerilog, and Verilog – or any combination in the same design.

“And because we also want to focus on the FPGA market, we’ve enhanced the FPGA flow in Release 6.0 by working closely with the FPGA tools providers and making the flow more tightly integrated.

“For the third important part piece of the new release – typically when people are going to close timing, they go through place-and-route and find the critical path after synthesis. What we’ve done in 6.0, however, is to provide the longest paths before synthesis, so the RTL designer can find and work on them before running a very expensive synthesis!”

Is Synopsys is offended by Blue Pearl’s efforts?

“Not at all,” Jeeawoody said. “In synthesis, there are two steps – the compilation phase and the analysis phase.

“We anticipate some of the changes they’re going to make, and give users an optimized SDC file. If you take the RTL and run synthesis, some of the internal paths may be optimized or removed, but if you don’t collaborate [with us] a lot of your constraints will be rejected and won’t be used.”

And why doesn’t Synopsys already do this? “A lot of innovation happens outside the big companies,” Jeeawoody said. “At Blue Pearl, we have the focus and drive to make this [technology] happen.

“The company started in 2004, and at that time the company wanted to try a lot of different technologies. We were talking with a set of different partners, determining where our sweet spot would be and which algorithms would work well. Finally in 2010 we found that sweet spot, and by 2011 were working on monetizing it. Our current partners are Altera and Synopsys, but we anticipate adding more to the list going forward.”

For RTL designers, how serious are the problems? Per Jeeawoody: “The first problem is serious: How do I get the right SDC?

“Today, it’s shooting in the dark, a reactive process: I have my design, I guess these are the constraints. If the timing’s not closed, I put in some more constraints and keep going. And what is Blue Pearl doing about it? We’re giving you all the false paths and multi-cycle paths.

“The second problem is also very serious – just yesterday we heard from a potential customer that they’re needing 30 to 40 iterations to closure. We give designers the SDCs early on in the design cycle, so they don’t have to iterate in the the dark.”

But what if designers really enjoy iterating?

“That’s unfortunate,” Jeeawoody admitted. “A long time ago, we did have a customer who liked going to get a cup of coffee during his iterations. Now there’s no time for coffee.

“Normally these days, people are laboring through the process and are glad to have our tools. With Release 6.0, they’ll be getting chips and different versions of their chips out there even more quickly.”

Tags: Altera, ASIC, Blue Pearl Software, CDC, clock-domain crossing, FPGA, RTL, RTL analysis, SDC, Shakeel Jeeawoody, SOC, Synopsys, Synopsys Design Constraints, SystemVerilog, Verific, Verilog, VHDL

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