Posts Tagged ‘SoC verification’
Tuesday, July 5th, 2016
If the title of today’s post sounds familiar, that’s not surprising. The most popular post in the history of The Breker Trekker blog, by a significant margin, was “An EDA Industry of Startups, Behemoths, Corner Stores, and Zombies?” published almost three years ago. I thought that it would be fun to revisit this topic in light of the changes in the EDA industry over the past three years. Have these changes fundamentally altered our world? Please read on to see.
I’ll begin, as I did in the original post, by noting that the EDA industry used to be divided into only three categories: major leaguers, minor leaguers, and startups. Nearly all EDA startups disappeared after three or four years, with three possible endgames: acquisition, initial public offering (IPO), or bankruptcy. The major leaguers, at one time or another, included Daisy, Mentor, Valid, Cadence, Synopsys, and Avant.
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Tags: acceleration, acquisition, applications, Atrenta, avant, behemoth, Breker, Cadence, corner store, coverage, debug, EDA, functional verification, jasper, M&A, major leaguer, mentor, merger, minor leaguer, reuse, SoC verification, startup, Synopsys, uvm
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Wednesday, June 29th, 2016
Over the more than three years of posts here on The Breker Trekker blog, you’ve seen us reference our TrekBox runtime component on many occasions. We mention it in many contexts: test case visualization, memory usage visualization, test case status, test case debugging, system-level coverage, performance analysis, I/O interfacing, UVM testbench control, and more. We’ve never had a post on TrekBox itself, so today we rectify that and fill in a few details that we haven’t discussed before.
Some of you are familiar with the term “trickbox” in the context of a simulation testbench. We found a nice concise definition of this term in an ARM patent: “Memory mapped (behavioral) test bench component to facilitate verification.” By writing to designated memory addresses, the processors in the design being verified can send messages to the testbench for various actions. Our TrekBox is of course a play on the “trickbox” name, and it provides many presents inside for those who open it.
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Tags: acceleration, applications, apps, bandwidth, Breker, cache coherency, coverage, debug, duration, EDA, emulation, FPGA prototyping, functional verification, graph, multi-SoC, multiprocessor, performance analysis, reuse, scenario model, simulation, SoC verification, system coverage, transactional, TrekApp, TrekBox, TrekSoC, TrekSoC-Si, UVC, uvm
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Wednesday, June 22nd, 2016
We have a saying here at Breker that the fundamental job of any EDA company in the functional verification space is to “find more bugs, more quickly.” A good verification solution increases design quality by finding more bugs, improves time to market by closing verification faster, or reduces project cost by requiring fewer resources. A great verification solution, which we strive to offer, does all three. Accordingly, we talk a lot about the type of design bugs we can find with less time and effort than traditional methods.
We have another saying at Breker: “A performance shortfall is a functional bug.” A lot of people differentiate between these two cases, but we don’t agree. The specification for your SoC describes its performance goals as well as its functionality. Not meeting your requirements for latency or throughout can render your SoC unsellable just as surely as a broken feature. So we also talk a lot about how our portable stimulus techniques generate test cases for performance verification.
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Tags: acceleration, applications, apps, bandwidth, Breker, cache coherency, coverage, duration, EDA, emulation, FPGA prototyping, functional verification, graph, latency, performance, performance analysis, reuse, scenario model, simulation, SoC verification, throughput, transactional, TrekApp, TrekBox, TrekSoC, TrekSoC-Si, UVC, uvm
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Thursday, June 9th, 2016
We’ve just wrapped up the 53rd annual Design Automation Conference (DAC), held for just the second time in Austin. As we mentioned in our show preview last week, Breker was founded in Austin so it’s always nice to return to our roots. With its live music, countless good BBQ joints, and sense of history, Austin is always a fun place to visit. The city has a large high-tech workforce, so we expected crowds similar to those in San Francisco or San Diego.
To be honest, the exhibition floor looked rather quiet at times. With the wide aisles and many attendees clustered around the Big Three EDA vendors and those booths with entertainment or giveaways, other parts of the floor seemed forgotten. Fortunately, our booth was on the major cross aisle and we had the industry momentum around portable stimulus in our favor, so we had a very good show. We’ll discuss our results as we fill in a few highlights from the four days we were there.
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Tags: Accellera, Agnisys, austin, Breker, cache coherency, cloud, cruise, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, NoC, PSWG, scenario model, Semifore, simulation, SoC verification, Synopsys, Trek, TrekSoC, uvm, Verdi, VIP
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Wednesday, June 1st, 2016
The Design Automation Conference (DAC) us nearly upon us once again, this year returning to Austin in just a few days. The first-ever DAC in Austin was held three years ago and it was by all accounts a really good show. It was nice seeing new faces who could carve out an afternoon to visit the exhibit floor but who couldn’t get permission to travel when DAC is elsewhere. We were very pleased by both the number of people who stopped by our booth and their level of interest in what we do.
As you may know, Breker was born in Austin and so it will be a bit of a homecoming for us to return again. Austin features many fun activities, especially musical in nature, and great BBQ restaurants. We’ll be glad to provide suggestions and pointers for these if you ask, but for today’s post we’d like to fill you in what we will be doing at the show this year. We welcome any comments or questions that you may have.
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Tags: Accellera, Agnisys, austin, Breker, cache coherency, cloud, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, NoC, PSWG, scenario model, Semifore, simulation, SoC verification, Synopsys, Trek, TrekSoC, uvm, Verdi, VIP
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Wednesday, May 25th, 2016
Last week on The Breker Trekker, we talked about path constraints and how they differ from other kinds of constraints commonly used in SoC design and verification. Our whole approach to verification is based on graph-based scenario models, and constraints on the paths through the graph are a natural way to control how our Trek family of products automatically generates test cases. It’s easy to eliminate some paths, focus on others, or bias the randomization of selections. We believe that path constraints should be a part of any portable stimulus solution that meets the forthcoming Accellera standard.
We have heard some people in the industry argue that path constraints are not needed, and that value constraints would suffice. While we agree that value constraints are a familiar concept from the UVM and other constrained-random approaches, we do not feel that they are the best way to control the scenarios generated from a portable stimulus model. In today’s post we will expand on the example from last week and show how path constraints can handle a more complex design better than value constraints.
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Tags: Accellera, application, Breker, functional verification, graph, graph-based, JPEG, MPEG, path constraint, PSWG, realistic use case, scenario model, simulation, SoC verification, SystemVerilog, test case generator, testbench, uvm, value constraint
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Thursday, May 19th, 2016
As engineers, we take great pride in defining our terms carefully and using them precisely to try to avoid ambiguity or confusion. Many engineering specifications start with a glossary of terms and sometimes even a taxonomy showing how they are related. Sometimes though, natural language being inherently ambiguous, we find that we have overloaded the meaning of certain words in a way that can lead to precisely the confusion we seek to avoid.
One such word is “constraint” because it is used in several different contexts in chip design and verification. In today’s post we would like to discuss path constraints on a graph-based scenario model. We will explain how they differ from other forms of constraints and why path constraints are essential for any portable stimulus solution, including the Trek family of products from Breker.
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Tags: Accellera, application, Breker, functional verification, graph, graph-based, JPEG, MPEG, path constraint, PSWG, realistic use case, scenario model, simulation, SoC verification, SystemVerilog, test case generator, testbench, uvm, value constraint
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Wednesday, May 11th, 2016
The title of last week’s post was a play on a Mark Twain quote. This week I draw from a more contemporary source: The Muppets. Some episodes of the legendary family TV show featured a skit called “Pigs in Space.” In my head I’m reading “SoCs in Space!” with the same booming intonation used on the show for “Pigs in Space” to lead into a somewhat more serious discussion about the use of advanced chips in extreme conditions.
My prompt for this particular post came not from TV, but from an announcement yesterday that VORAGO Technologies is offering an ARM-based microcontroller (MCU) “designed specifically for radiation and extreme temperature operation without up-screening.” In other words, they ship an MCU that’s ready to use in such traditionally challenging environments as automobiles and industrial controllers as well as, yes, space. That got me thinking about even more complex chips such as SoCs and the extreme conditions they might have to face.
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Tags: Breker, bring-up lab, C/C++, cache coherency, constraints, emulation, ESL, FPGA, functional verification, graph, graph-based, military grade, multi-SoC, prototyping, rad-hardened, radiation-hardened, realistic use case, scenario model, SoC verification, space, system-on-chip, test case generator, test cases
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Thursday, May 5th, 2016
With a nod to Mark Twain, this week I’d like to comment on a recent three–part series with the provocative title “Are Simulation’s Days Numbered?” The articles were transcribed from one of the “experts at the table” events that SemiconductorEngineering does so well. Breker wasn’t involved in this particular roundtable, but I enjoyed reading the series and found that it stirred up some thoughts. As a blogger, of course I’m going to share them with you and I hope you enjoy them in turn.
Let’s get this out of the way immediately: in three parts and more than 5,000 words, there was no mention of portable stimulus. That might not seem too surprising given the title, but in fact verification portability both from IP to system and from simulation to hardware arose during the discussion. So I’ll comment on that but, given my background as a vendor of formal EDA tools and reusable IP blocks, there are a few other topics that also piqued my interest.
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Tags: Accellera, Adapt IP, Breker, bring-up lab, C/C++, cache coherency, Cadence, constraints, emulation, ESL, FPGA, functional verification, graph, graph-based, IP, multi-SoC, OneSpin, prototyping, PSWG, realistic use case, Rizzatti, scenario model, simulation, SoC validation, SoC verification, Synopsys, system-on-chip, SystemVerilog, test case generator, test cases
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Tuesday, April 26th, 2016
Ever since Accellera started the Portable Stimulus Working Group (PSWG), this emerging technology has generated a lot of buzz both within the EDA industry and among our semiconductor and systems customers. As the pioneer in this technology we get a lot of questions about what portable stimulus is, why it is different from the Universal Verification Methodology (UVM) and other established approaches, and why anyone would need it.
We’ve devoted quite a few posts to this topic in The Brekker Treker blog, stretching back two years to when Accellera first set up a proposed working group (PWG) to survey the industry and decided whether standardization of portable stimulus was feasible and desirable. Given the many posts scattered throughout the past two years, we thought that we would take this opportunity to give readers new to this topic a guided tour of the information that we have available.
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Tags: Accellera, Breker, bring-up lab, C/C++, cache coherency, Cadence, Cavium, constraints, dvcon, DVCon India, EDACafe, emulation, ESL, FPGA, functional verification, graph, graph-based, mentor, multi-SoC, prototyping, PSWG, scenario model, simulation, SoC validation, SoC verification, system-on-chip, SystemVerilog, test case generator, test cases
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