Posts Tagged ‘scenario model’
Tuesday, December 22nd, 2015
In last week’s blog post, I reported from the recent 16th International Workshop on Microprocessor Test and Verification (MTV) in Austin. I focused mostly on the panel “Portable Stimulus and Testbenches – Possibilities or Wishful Thinking?” that included representatives from ARM, Cadence, Mentor, Synopsys, Freescale (now NXP), and Breker (yours truly). The panel was most enjoyable, but only one of several highlights for me at MTV.
This week, I’d like to touch briefly on some of the talks and topics on the technical program that caught my ear. These reflected a number of research frontiers for verification as well as several real-world case studies of SoC design projects tackling tough verification challenges. Perhaps the best moment for me was hearing Altera, one of our customers, describe how they used our products successfully on a recent design.
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Tags: Accellera, AMD, ARM, austin, Avago, Breker, Cadence, EDA, FPGA, Freescale, functional verification, graph, graph-based, mentor, MTV, node, NVIDIA, portable stimulus, PSWG, scenario model, simulation, SoC verification, Sudoku, Synopsys, test generator
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Wednesday, December 16th, 2015
Do you want to hear all the behind-the-scenes dirt from a workshop on the future of the MTV cable channel? Well, you’ll have to look elsewhere. “MTV” in this case means the International Workshop on Microprocessor Test and Verification, which celebrated its 16th incarnation in Austin two weeks ago. Although the name of the workshop has officially expanded to “Microprocessor and SOC Test and Verification” rest assured that the delightfully ambiguous abbreviation “MTV” will remain.
This was only my second time at this event, but I wish that I had been able to attend more. The setting is the top floor of the Hyatt Regency, with great views of Lady Bird Lake (formerly Town Lake) and downtown Austin. However, I noticed that recent high-rise construction has now blocked the sight of the Texas State Capitol from the hotel. The view might be distracting if not for the fact that the technical committee put together an interesting and diverse program, including a panel on portable stimulus.
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Tags: Accellera, ARM, austin, Breker, Cadence, EDA, emulation, FPGA, Freescale, functional verification, graph, graph-based, horizontal reuse, mentor, MTV, node, portable stimulus, PSWG, scenario model, silicon, simulation, SoC verification, Synopsys, test generator, vertical reuse
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Thursday, December 10th, 2015
The past two weeks, we’ve been having a bit of fun playing alchemist and letting readers in on some of the deep, dark secrets of graph-based verification technology. This week, we conclude the series by showing some additional capabilities for our scenario models that are easy to control and view in a graph visualization. Our point is, of course, that graphs are a natural way to represent data flow and verification intent with no advanced degrees from MIT, IIT, or Hogwarts required.
As a quick reminder, graph-based scenario models begin with the end in mind and show all possible paths to create each possible outcome for the design. They look much like a reversed data-flow diagram, with outcomes on the left and inputs on the right. Breker’s Trek family can traverse the graph from left to right, randomizing selections to automatically generate test cases tailored to run in any target platform. Today, we continue using our example of a scenario model to verify that an automobile can move forward or stop.
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Tags: Accellera, Breker, constraints, cross-coverage, EDA, functional verification, goal, graph, graph-based, horizontal reuse, node, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, system-level coverage, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
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Thursday, December 3rd, 2015
Last week, we began exploring some of the ancient, mysterious powers of graph-based scenario models to show their power for verification and ability to capture the verification space, many aspects of the verification plan, and critical coverage metrics. We’re just kidding about the first part; there’s nothing at all mystical or magical about graphs. In fact, this series of posts is intended to show the opposite and demonstrate with a easy-to-follow example the value of graphs.
As we noted in our last post, graph-based scenario models are simple in concept: they begin with the end in mind and show all possible paths to create each possible outcome for the design. They look much like a reversed data-flow diagram, with outcomes on the left and inputs on the right. An automated tool such as Breker’s Trek family can traverse the graph from left to right, randomizing selections to generate test cases that can run in any target platform.
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Tags: Accellera, Breker, constraints, EDA, functional verification, goal, graph, graph-based, horizontal reuse, node, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
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Tuesday, November 24th, 2015
If there’s one thing that Breker is known for, it’s the use of graphs for verification. From our earliest days, we harnessed the abstraction and expressive power of graph-based scenario models to capture the verification space, many aspects of the verification plan, and critical coverage metrics. As we reported in a post a few weeks ago, it looks certain that the industry will follow our lead and base the upcoming standard from Accellera‘s Portable Stimulus Working Group (PSWG) on a graph representation.
As discussions have proceeded both within the PSWG and informally with interested parties, it has become clear that “graph” may not mean the same thing to all people. Our view of graphs is precisely defined in a way that makes it easy for users to create them and feasible for our tools to generated complex, multiprocessor test cases from them. Most of the key concepts can be communicated easily by the use of a familiar example, which we will begin in today’s post and continue next week.
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Tags: Accellera, Breker, EDA, functional verification, goal, graph, graph-based, horizontal reuse, node, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
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Wednesday, October 28th, 2015
Those of us of a certain age will remember the secret decoder rings promoted by various products and TV shows. They generally used a simple substitution code to map letters to numbers. According to Wikipedia these have been offered as recently as 2000, so perhaps they are known to younger readers as well. What’s germane to today’s blog post is that formal services company Oski Technology has cleverly used this device as a graphical element in promoting its “Decoding Formal” Club series.
I’ve reported before from these events, which I believe have been very effective at advocating for formal analysis, sharing tricks and techniques, and demystifying what was once regarded as an arcane academic approach to verification. Last week I attended another Decoding Formal Club forum and, as usual, was impressed by the depth of the presentations. Since formal is always a popular topic among readers of The Breker Trekker, I’m going to share a few highlights from that afternoon.
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Tags: Accellera, ARM, assertions, Breker, Broadcom, cache coherency, constraints, EDA, formal, functional verification, graph-based verification, NVIDIA, oski, portable stimulus, properties, scenario model, SoC verification, standards, Trek, TrekApp, TrekSoC
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Friday, October 16th, 2015
We’re coming up to the two-and-a-half-year anniversary for The Breker Trekker, with 124 published posts. Initially I promised a post every other week, but after looking at the viewing patterns I quickly realized that I had to publish every week to establish a consistent audience. There’s always something to talk about in this fast-paced world, whether something new at Breker, standards activity, observations about the EDA industry, or analysis of the customers who drive our business.
Today I’d to acknowledge a second Breker blog that has actually been around longer than this one. Just over three years ago, Breker board of directors member Michel Courtoy started a series of posts in Electronic Engineering Times to offer advice to startups. He has published 28 such posts, and has covered an amazing amount of territory. I suppose that I should have done some “cross-promotion” earlier, but at this point I would like to highlight some of Michel’s sage advice. (more…)
Tags: Breker, EDA, EE Times, Electronic Engineering Times, functional verification, graph, graph-based, Michel Courtoy, portable stimulus, realistic use case, scenario model, simulation, SoC verification, software, software-driven verification, startups, test generator
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Friday, October 2nd, 2015
Anyone who has followed Breker for any length of time knows that our key technology is the ability to generate both Universal Verification Methodology (UVM) testbench transactions and C test cases running on SoC embedded processors automatically from graph-based scenario models. Yes, that’s a long sentence but it’s most of the “elevator pitch” that we might deliver to a potential investor or to a visitor at a trade show booth asking what we do.
For the purposes of today’s post, note that graphs are the root of the solution we provide. Ten years ago, when we first began talking about the idea of graphs as the basis for functional verification of complex chip designs, we were the proverbial pioneer with arrows in our back. But many successful customer engagements and the ever-rising need for better verification have validated our position. Graphs are clearly the “next big thing” in verification and we’d like to explain why.
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Tags: Accellera, Breker, Cadence, EDA, functional verification, graph, graph-based, horizontal reuse, mentor, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
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Wednesday, September 23rd, 2015
Anyone who reads The Breker Trekker from time to time needs no convincing from me that verification is a huge challenge for today’s complex chips. Breker’s Trek family of products exists, along with dozens if not hundreds of other EDA products, specifically to address functional verification. There are more technologies, tools, platforms, libraries, and methodologies than any one verification engineer can possibly learn and use on a day-to-day basis.
Why this diversity of solutions? As I first observed in Electronic Engineering Times nearly a decade ago, there is no silver bullet for verification. The problem is both so broad and so deep that no single tool or technology will ever satisfy the need. It takes a mix of solutions, guided by methodologies, to have any chance of first-silicon success. Low-power verification is an area where this is especially true, and unfortunately there is no silver bullet to be found here either.
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Tags: 1801, Accellera, ARM, Breker, Common Power Format, CPF, DV, EDA, emulation, formal analysis, functional verification, graph, graph-based, mentor, portable stimulus, scenario model, simulation, SoC verification, standards, Synopsys, test generation, TrekSoC, TrekSoC-Si, Unified Power Format, UPF, use cases
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Wednesday, September 16th, 2015
Last week, we discussed the details of a noteworthy press release that we issued with Cadence and Mentor Graphics announcing a joint contribution to the Portable Stimulus Working Group (PSWG) of Accellera Systems Initiative. As we expected, this release stirred up a lot of interest in portable stimulus. The timing was perfect, both because of today’s deadline for contributions to the PSWG and because of last week’s DVCon India conference. I’d like to provide some updates on both activities.
First of all, the three companies did upload our joint contribution document to the PSWG internal Web site today in time for the deadline. Please note that, as per the rules for Accellera and most other standards groups, working documents are not available to the general public. If you’d like to see the contribution and follow the evolution of the standard, please consider joining the PSWG. If your company is not yet a member of Accellera, then please alert your standards manager to the benefits of participation.
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Tags: Accellera, Breker, Cadence, DVCon India, EDA, functional verification, graph, graph-based, horizontal reuse, mentor, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, SystemVerilog, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
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