Posts Tagged ‘Cadence’
Monday, March 10th, 2014
In our last two posts, we talked about the 2014 edition of the Design & Verification Conference & Exhibition, DVCon, in San Jose. Now that the show is history, lots of bloggers are summarizing their experience. Since I thought that this was an excellent event all around, allow me to join the chorus of voices praising DVCon 2014.
Here at Breker, our biggest effort goes toward the exhibition. Although it’s a relatively small booth and exhibit floor, we do want to put our best foot forward. So we had all-new signage this year updating attendees on our products and their capabilities. We also showed a very different demo from last year, with our TrekSoC-Si product generating a test case, downloading it into a commercial SoC (a TI OMAP4430), and running in the actual chip. We chose to repeat our very popular giveaway from DAC: a combined flashlight and distress whistle that will come in handy if you perform inadequate SoC verification and hit an iceberg.
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Tags: Breker, Cadence, dvcon, EDA, emulation, functional verification, graph, mentor, reuse, scenario model, simulation, SoC verification, test generation, TrekSoC-Si
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Tuesday, February 25th, 2014
Next week (March 3-6) marks the return of the most important annual event for verification engineers: the Design & Verification Conference & Exhibition 2014, better known as DVCon. Its home remains the DoubleTree hotel in San Jose, a Silicon Valley landmark and site of many interesting conferences going back to its original days as the Red Lion Inn. Breker will be there in force, so we’d like to tell you about our activities as well as preview the technical program.
Of course, Breker will be participating in the exhibition portion of the show. This has expanded from previous years. The exhibit floor will be open on Tuesday (March 4) and Wednesday (March 5) from 2:30pm to 6:00pm as usual. However, a special preview on Monday from 5:00pm to 7:00pm has been added this year. You’ll have plenty of time to stop by to visit Breker in booth number 902 and (if you must) perhaps some other vendors as well.
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Tags: Breker, Cadence, dvcon, EDA, emulation, functional verification, graph, mentor, panels, scenario model, simulation, SoC verification, Synopsys, system coverage, TrekSoC, TrekSoC-Si
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Tuesday, November 26th, 2013
The Breker Trekker has been publishing for about seven months now, with 32 posts to date, so running just about once a week. When we started, we committed a new post every two weeks so we’ve been running well ahead of our own expectations. We’re very happy with the growth of our readership and we’d like to take this chance to thank every one of you reading this.
Frankly, we have not been as successful at driving an ongoing dialogue via comments. We’ve had a few comments here and there but not nearly as many as we would like to see. So for this week’s post we’re trying something different: posing a question directly to our readers and heartily encouraging all of you to share your thoughts by leaving a comment at the bottom. Today’s topic: which conferences and trade shows do you find most useful?
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Tags: arrm techcon, Cadence, CDNLive, conference, dac, dvcon, EDA, functional verification, SNUG, Synopsys
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Tuesday, October 1st, 2013
Last week our friends at Cadence held the grandly named System-to-Silicon Summit not in some grand hotel, but rather at their San Jose offices. While Breker folks of course were not invited, we were curious as to how much SoC verification was addressed. Fortunately, Cadence writer and EDA legend Richard Goering has provided a very nice summary of a panel at the event dealing very much with topics of interest to us and our customers.
Within three paragraphs of Richard’s article, journalist Brian Bailey is already talking about top-down verification with “use cases.” Cadence’s Ziv Binyamini continued the topic by saying “the only way to define the requirements is against the use cases.” Jim Hogan mentioned “scenarios” for defining system behavior. There was also discussion about use cases being valuable for embedded software as well as hardware. To anyone who knows anything about Breker, this all sounds very familiar.
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Tags: application scenario, Breker, Cadence, functional verification, scenario model, test case, test generation, top-down, use cases
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Tuesday, August 27th, 2013
From the blog stats it seems clear that late August is a slow time with lots of folks on vacation, so I’ll take a break from the heavy technical topics to chat about the industry. Long before I worked for an EDA company, I was an active participant as a user of EDA tools and as a CAD manager tasked with evaluating them and integrating them together. In that role, I loved working with interesting startups that had new ideas for electronic development.
It was part of my job to follow the EDA industry closely so that we could choose our tool investments based on both strength of technology and likelihood of vendor success. It seemed to me that the industry was divided into only three categories: major leaguers, minor leaguers, and startups. I observed that nearly all EDA startups disappeared after three or four years, with three possible endgames: acquisition, initial public offering (IPO), or bankruptcy.
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Tags: avant, behemoth, Breker, Cadence, corner store, EDA, functional verification, jasper, major leaguer, mentor, minor leaguer, SoC verification, startup, Synopsys
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Monday, August 5th, 2013
Back in March I published an opinion piece in Chip Design magazine about redefining “DAC” from “Design Automation Conference” to “Development Automation Conference” and “EDA” from “Electronic Design Automation” to “Electronic Development Automation” to reflect reality. It generated a few comments and got a few people talking but that’s as far as it went.
I certainly didn’t expect a groundswell of support or an overnight change, but I was serious about my reasoning. I think that describing the incredibly complex development process for electronic products as “design” is outdated and not representative of the wide range of skills required.
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Tags: Breker, Cadence, CDNLive, dac, dvcon, EDA, EDAC, functional verification, SNUG, Synopsys
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Tuesday, July 2nd, 2013
A year or two ago, cloud computing was a hot topic at EDA events and conferences. The industry’s largest player, Synopsys, talked a lot about running their EDA tools in the cloud and claimed a great deal of customer interest in this area. Earlier this year, CEO Aart de Geus was quoted as saying that “Synopsys had made $0 on it.” What happened? Is the idea of EDA in the cloud dead? What are the issues preventing its adoption?
In talking to customers and reading related articles, I’ve heard of several reasons why the cloud is not yet a factor for EDA. One practical issue is that EDA vendors are not sure how to price cloud-based licenses. If the customer motivation to move to the cloud is to more easily handle infrequently used tools or to provide peak capacity for frequently used tools, indeed the wrong pricing model could cost the vendor money. One technical issue is that some EDA tools are interactive and would be painful to use over the Internet.
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Tags: Breker, Cadence, cloud computing, EDA, functional verification, SoC verification
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Thursday, May 2nd, 2013
I’m dropping a bonus post in the middle of our usual two-week schedule to share some thoughts about Joe Costello’s talk with Jim Hogan at a special EDAC event last night. For those who may not follow EDA as intently as we do:
- EDAC is the Electronic Design Automation Consortium, the main trade group for the EDA industry
- Jim Hogan is a well-known EDA investor and entrepreneur
- Joe Costello is the former President and CEO of Cadence, now leading Orb Networks
These facts don’t capture the almost mythical role that Joe Costello plays in the EDA industry. I joined Cadence long after he had departed, but in my five years there I’ll bet I heard his name brought up nearly every week. His stint as the head of Cadence is inextricably intertwined with the glory days of the EDA industry. Many are nostalgic for those days and many have urged him to come back to the EDA fold. He has done so to some extent through his investments.
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Tags: Breker, Cadence, Costello, EDA, Hogan, SoC verification
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