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 The Breker Trekker
Tom Anderson, VP of Marketing
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »

Hey, the EDA World Is Starting to Speak Breker’s Language!

October 1st, 2013 by Tom Anderson, VP of Marketing

Last week our friends at Cadence held the grandly named System-to-Silicon Summit not in some grand hotel, but rather at their San Jose offices. While Breker folks of course were not invited, we were curious as to how much SoC verification was addressed. Fortunately, Cadence writer and EDA legend Richard Goering has provided a very nice summary of a panel at the event dealing very much with topics of interest to us and our customers.

Within three paragraphs of Richard’s article, journalist Brian Bailey is already talking about top-down verification with “use cases.” Cadence’s Ziv Binyamini continued the topic by saying “the only way to define the requirements is against the use cases.” Jim Hogan mentioned “scenarios” for defining system behavior. There was also discussion about use cases being valuable for embedded software as well as hardware. To anyone who knows anything about Breker, this all sounds very familiar.

The definition of application scenarios that represent realistic use cases for the chip is at the heart of Breker’s approach to SoC verification. We’ve observed that customers’ full-chip testbenches, at best, verify that single IP blocks are stitched in correctly. Some SoC projects tape out at that point, using the dangerous “stitch and ship” method likely to leave system-level bugs lurking in the design.

Other project teams hand-write software tests to run on the SoC’s embedded processors in simulation and perhaps acceleration. These too are almost always focused on testing individual IP blocks rather than stringing them together into application use cases. The remaining SoC verification teams realize that something better is needed, and invest in Breker’s TrekSoC technology.

Our focus is entirely on capturing end-to-end use cases in graph-based scenario models and using this information to automatically generate self-verifying C test cases that run many randomized scenarios. Our recent blog post used the example of a digital camera to show the different use cases and how TrekSoC exercises them all thoroughly. If the camera has multiple processors, or its processors have multiple threads, TrekSoC generates even more complex test cases with multiple scenarios running in parallel.

Fellow EDA Cafe contributor Peggy Aycinena has published a very funny commentary “inspired” by this same panel at the Cadence event. She also mentions top-down verification and use cases several times. She quotes the panelists talking about the concept of the “intelligent testbench” that, among other things, abstracts full-chip SoC verification so that the same IP blocks are not re-verified again and again. Breker was actually mentioned in the panel as a company who has “good tools” in this area, a detail curiously missing from the Cadence coverage.

So it all comes down to defining the use cases for the SoC, and we were pleased that the participants in the panel agree. We’ve been leading the charge in this space for several years now and it’s gratifying to see the industry not just taking notice but agreeing with us. If you like what others are saying about top-down verification, use cases, and scenarios, be sure and talk to Breker. As the old saying goes, we invented this stuff.

Tom A.

The truth is out there … sometimes it’s in a blog.

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