The Breker Trekker
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »
Sound the Trumpets! It’s DVCon Time Again!
February 25th, 2014 by Tom Anderson, VP of Marketing
Next week (March 3-6) marks the return of the most important annual event for verification engineers: the Design & Verification Conference & Exhibition 2014, better known as DVCon. Its home remains the DoubleTree hotel in San Jose, a Silicon Valley landmark and site of many interesting conferences going back to its original days as the Red Lion Inn. Breker will be there in force, so we’d like to tell you about our activities as well as preview the technical program.
Of course, Breker will be participating in the exhibition portion of the show. This has expanded from previous years. The exhibit floor will be open on Tuesday (March 4) and Wednesday (March 5) from 2:30pm to 6:00pm as usual. However, a special preview on Monday from 5:00pm to 7:00pm has been added this year. You’ll have plenty of time to stop by to visit Breker in booth number 902 and (if you must) perhaps some other vendors as well.
Our focus in the booth is the many new features added to our flagship TrekSoC product since last year’s show as well as the TrekSoC-Si product we introduced late in 2013. You can see a live demo with TrekSoC-Si generating a test case, downloading it into a commercial SoC (a TI OMAP4430), and running in the actual chip. This shows our ability to support all verification platforms, from ESL and RTL simulation through acceleration, emulation, FPGA prototyping, and silicon. We’ll be glad to demonstrate other aspects of our products, discuss your verification needs, or just chat about the SoC industry.
Breker is also participating in the technical program, with Tom Anderson on the panel “Is Software the Missing Piece In Verification?” Wednesday from 8:30am to 9:45am. This should be a very lively debate since it includes every EDA vendor involved in graph-based verification plus a few folks who may have different proposals for improving coverage while reducing manual effort. We’d be delighted if you can join us for this session in addition to visiting our booth.
Elsewhere on the technical program, there has been an interesting shift. Over the years, DVCon has become much more associated with verification than design. In fact, some people thought that “DV” stood for “Design Verification” rather than “Design & Verification” in the conference name. At the same time that DVCon reduced its design content, DesignCon all but eliminated verification sessions. For most Silicon Valley engineers, DesignCon was all about design and DVCon was all about verification.
This year, general chair Stan Krolikoski decided that DVCon should focus on high-level design as well as verification. The results are clear in the number of sessions and papers that contain “Design” in their titles. However, the expanded scope does not seem to have come at any cost to the verification content, which remains both strong and diverse. We’re especially intrigued by the two sessions on “Advance Methodologies and Testbenches” (although surely that’s a typo that should be “Advanced”).
So that’s our clarion call for the most exciting verification event of the year. Please join us if you possibly can!
The truth is out there … sometimes it’s in a blog.
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