Posts Tagged ‘application’
Wednesday, May 25th, 2016
Last week on The Breker Trekker, we talked about path constraints and how they differ from other kinds of constraints commonly used in SoC design and verification. Our whole approach to verification is based on graph-based scenario models, and constraints on the paths through the graph are a natural way to control how our Trek family of products automatically generates test cases. It’s easy to eliminate some paths, focus on others, or bias the randomization of selections. We believe that path constraints should be a part of any portable stimulus solution that meets the forthcoming Accellera standard.
We have heard some people in the industry argue that path constraints are not needed, and that value constraints would suffice. While we agree that value constraints are a familiar concept from the UVM and other constrained-random approaches, we do not feel that they are the best way to control the scenarios generated from a portable stimulus model. In today’s post we will expand on the example from last week and show how path constraints can handle a more complex design better than value constraints.
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Tags: Accellera, application, Breker, functional verification, graph, graph-based, JPEG, MPEG, path constraint, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, SystemVerilog, test case generator, testbench, uvm, value constraint
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Thursday, May 19th, 2016
As engineers, we take great pride in defining our terms carefully and using them precisely to try to avoid ambiguity or confusion. Many engineering specifications start with a glossary of terms and sometimes even a taxonomy showing how they are related. Sometimes though, natural language being inherently ambiguous, we find that we have overloaded the meaning of certain words in a way that can lead to precisely the confusion we seek to avoid.
One such word is “constraint” because it is used in several different contexts in chip design and verification. In today’s post we would like to discuss path constraints on a graph-based scenario model. We will explain how they differ from other forms of constraints and why path constraints are essential for any portable stimulus solution, including the Trek family of products from Breker.
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Tags: Accellera, application, Breker, functional verification, graph, graph-based, JPEG, MPEG, path constraint, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, SystemVerilog, test case generator, testbench, uvm, value constraint
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Wednesday, March 9th, 2016
In last week’s post on The Breker Trekker we summarized activities at the Design and Verification Conference and Exhibition (DVCon) in San Jose, including a brief mention of the “Redefining ESL” panel on Wednesday morning. I attended this session and took detailed notes in anticipation of blogging about it, but in the process gave some thought to my own opinions about the electronic system-level (ESL) domain and how they intersect with those of the panel participants.
The panel was organized by Dave Kelf of OneSpin Solutions and PR guru Nanette Collins, and moderated by Brian Bailey of SemiconductorEngineering. Brian is a long-time observer of the ESL market so I expected him to ask some tough questions. He opened by remarking that the term is generally credited to the late EDA analyst Gary Smith. Many of us who knew Gary sometimes teased him a bit on his regular pronouncements that “this will be the year of ESL.”
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Tags: Accellera, application, Breker, bring-up lab, Cadence, dvcon, emulation, ESL, FPGA, functional verification, graph, high-level synthesis, HLS, Imperas, mentor, node coverage, OneSpin, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, Synopsys, system-on-chip, test case generator, test cases, Universal Verification Methodology, use-case coverage, uvm, virtual platform, virtual prototype
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Thursday, March 3rd, 2016
We’ve just returned from our most important trade show of the year: the Design and Verification Conference and Exhibition (DVCon) in San Jose. Sure, DAC is a bigger show, but it covers all of EDA and so lacks the front-end digital focus of DVCon. We previewed the event over our last few blog posts and today we’d like to summarize what happened and make a prediction or two about how this particular DVCon will affect the industry.
The biggest news for us was that portable stimulus seemed to be on everyone’s lips this year. Many of the engineers who stopped by to visit our booth had heard the term and were aware that the Accellera Portable Stimulus Working Group (PSWG) is developing a standard. If they didn’t know what portable stimulus was, they almost surely knew by the end of the show.
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Tags: Accellera, application, Breker, bring-up lab, cache coherency, Cadence, Cavium, dvcon, emulation, ESL, FPGA, functional verification, graph, graph-based, mentor, multi-SoC, node coverage, path coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekApp, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm
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Wednesday, February 24th, 2016
We hope that the title of this blog post piqued your interest, because we don’t believe that we’ve seen anyone anywhere claiming to do automated multi-SoC verification at this level. Two weeks ago, we previewed next week’s Design and Verification Conference and Exhibition (DVCon) in San Jose. We highlighted one particular talk being co-presented by Breker and Cavium on “Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC” in the 9:00-10:30 a.m. session on Tuesday, March 1.
We teased you with the statement that this talk will describe “generating test cases for a multi-SoC configuration with well over 100 cores” and it’s time to tell you a bit more now that we have issued a press release on our project with Cavium. Of course, we need to reserve some of the details for the paper in the DVCon proceedings and the talk itself so that new material is being presented at the conference. We heartily encourage you at attend the show and hear for yourself.
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Tags: application, Breker, bring-up lab, cache coherency, Cavium, dvcon, emulation, FPGA, functional verification, graph, graph-based, multi-SoC, node coverage, path coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm
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Friday, February 19th, 2016
In last week’s post, we provided a preview of the program at the annual Design and Verification Conference and Exhibition (DVCon) in San Jose, coming up in ten days. We mentioned some of the interesting talks and other activities there, and focused in particular on “Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC” on Tuesday morning. The paper for this session was co-authored by Breker and Cavium, and both companies will present together at DVCon.
The paper and presentation describe the use of our Cache Coherency TrekApp and TrekSoC-Si to automatically generate self-checking, portable test cases for more than 100 CPU cores in a multi-SoC configuration in the Cavium bring-up lab. To set the stage for this story, today we’d like to revisit some of the reasons why cache coherency is so hard to verify and why an automated approach is the best solution.
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Tags: application, Breker, bring-up lab, cache coherency, Cavium, dvcon, emulation, FPGA, functional verification, graph, graph-based, MOESI, multi-SoC, node coverage, path coverage, portable stimulus, protocol, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm
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Wednesday, February 10th, 2016
Regular readers of The Breker Trekker know that we like to preview, review, and dissect technical conferences and trade shows that are of interest to verification engineers. Perhaps the conference we’ve covered the most has been the annual Design and Verification Conference and Exhibition (DVCon) in San Jose. As far as we know, this is the biggest event anywhere focused on digital and system design and verification, a nice complement to the analog-ish DesignCon.
As a matter of fact, DVCon has become so successful that there are now regional conferences in India and Europe in addition to the U.S. show. We’ve strongly supported DVCon India, including serving for all three years on the Promotions Committee, and have participated in DVCon Europe as well. But those are a bit in the future; DVCon (U.S.) 2016 is coming up in a just a few weeks. The program is online now, so we thought we’d review it and suggest some sessions of possible interest.
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Tags: application, Breker, bring-up lab, cache coherency, Cavium, dvcon, emulation, FPGA, functional verification, graph, graph-based, multi-SoC, node coverage, path coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm
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Wednesday, February 3rd, 2016
For more than four years now, Breker has branded itself as “The SoC Verification Company” and many people acknowledge our expertise in this domain. As we have discussed before on The Breker Trekker, our initial products focused on generating purely transactional tests for a simulation testbench, usually compliant with the Accellera Universal Verification Methodology (UVM) standard. When we extended our products to generate C code that runs on the embedded processors found within SoCs, we delivered on our “tagline” promise.
Since our early focus on simulating an SoC, we have expanded our technology and our product line to generate C test cases that run on embedded processors in emulation, FPGA prototypes, and actual silicon in the bring-up lab. In talking about what we do, we struggle to choose between “SoC” and “system” since for many of our customers the terms are synonymous. But we also have users verifying multi-SoC systems, and today we’d like to address that topic.
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Tags: application, Breker, bring-up lab, cache coherency, dvcon, emulation, FPGA, functional verification, graph, graph-based, multi-SoC, node coverage, path coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm
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Wednesday, January 6th, 2016
It’s been more than a year since we presented the Breker view of system coverage in detail, so it’s time to revisit the topic. We first defined the notion of system coverage as measuring which realistic, system-level application scenarios have been exercised using the existing test cases. We then demonstrated how our graph-based scenario models are ideally suited to capture system coverage metrics and fine-tune them using graph constraints if needed.
More recently, we noted that the term “use cases” has become more widespread and introduced the example of a digital camera SoC to show the types of use cases that should be exercised. The measurement for this exercise is also system coverage, so the bottom line is that all these terms are really talking about the same thing. Using a regular expression, we might say:
[application|realistic] (scenario|use-case) coverage = system coverage
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Tags: Accellera, application, Breker, functional verification, graph, graph-based, node coverage, path coverage, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, system coverage, test case generator, Universal Verification Methodology, use-case coverage, uvm
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