Posts Tagged ‘Accellera’
Wednesday, May 25th, 2016
Last week on The Breker Trekker, we talked about path constraints and how they differ from other kinds of constraints commonly used in SoC design and verification. Our whole approach to verification is based on graph-based scenario models, and constraints on the paths through the graph are a natural way to control how our Trek family of products automatically generates test cases. It’s easy to eliminate some paths, focus on others, or bias the randomization of selections. We believe that path constraints should be a part of any portable stimulus solution that meets the forthcoming Accellera standard.
We have heard some people in the industry argue that path constraints are not needed, and that value constraints would suffice. While we agree that value constraints are a familiar concept from the UVM and other constrained-random approaches, we do not feel that they are the best way to control the scenarios generated from a portable stimulus model. In today’s post we will expand on the example from last week and show how path constraints can handle a more complex design better than value constraints.
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Tags: Accellera, application, Breker, functional verification, graph, graph-based, JPEG, MPEG, path constraint, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, SystemVerilog, test case generator, testbench, uvm, value constraint
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Thursday, May 19th, 2016
As engineers, we take great pride in defining our terms carefully and using them precisely to try to avoid ambiguity or confusion. Many engineering specifications start with a glossary of terms and sometimes even a taxonomy showing how they are related. Sometimes though, natural language being inherently ambiguous, we find that we have overloaded the meaning of certain words in a way that can lead to precisely the confusion we seek to avoid.
One such word is “constraint” because it is used in several different contexts in chip design and verification. In today’s post we would like to discuss path constraints on a graph-based scenario model. We will explain how they differ from other forms of constraints and why path constraints are essential for any portable stimulus solution, including the Trek family of products from Breker.
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Tags: Accellera, application, Breker, functional verification, graph, graph-based, JPEG, MPEG, path constraint, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, SystemVerilog, test case generator, testbench, uvm, value constraint
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Thursday, May 5th, 2016
With a nod to Mark Twain, this week I’d like to comment on a recent three–part series with the provocative title “Are Simulation’s Days Numbered?” The articles were transcribed from one of the “experts at the table” events that SemiconductorEngineering does so well. Breker wasn’t involved in this particular roundtable, but I enjoyed reading the series and found that it stirred up some thoughts. As a blogger, of course I’m going to share them with you and I hope you enjoy them in turn.
Let’s get this out of the way immediately: in three parts and more than 5,000 words, there was no mention of portable stimulus. That might not seem too surprising given the title, but in fact verification portability both from IP to system and from simulation to hardware arose during the discussion. So I’ll comment on that but, given my background as a vendor of formal EDA tools and reusable IP blocks, there are a few other topics that also piqued my interest.
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Tags: Accellera, Adapt IP, Breker, bring-up lab, C/C++, cache coherency, Cadence, constraints, emulation, ESL, FPGA, functional verification, graph, graph-based, IP, multi-SoC, OneSpin, portable stimulus, prototyping, PSWG, realistic use case, Rizzatti, scenario model, simulation, SoC validation, SoC verification, Synopsys, system-on-chip, SystemVerilog, test case generator, test cases
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Tuesday, April 26th, 2016
Ever since Accellera started the Portable Stimulus Working Group (PSWG), this emerging technology has generated a lot of buzz both within the EDA industry and among our semiconductor and systems customers. As the pioneer in this technology we get a lot of questions about what portable stimulus is, why it is different from the Universal Verification Methodology (UVM) and other established approaches, and why anyone would need it.
We’ve devoted quite a few posts to this topic in The Brekker Treker blog, stretching back two years to when Accellera first set up a proposed working group (PWG) to survey the industry and decided whether standardization of portable stimulus was feasible and desirable. Given the many posts scattered throughout the past two years, we thought that we would take this opportunity to give readers new to this topic a guided tour of the information that we have available.
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Tags: Accellera, Breker, bring-up lab, C/C++, cache coherency, Cadence, Cavium, constraints, dvcon, DVCon India, EDACafe, emulation, ESL, FPGA, functional verification, graph, graph-based, mentor, multi-SoC, portable stimulus, prototyping, PSWG, scenario model, simulation, SoC validation, SoC verification, system-on-chip, SystemVerilog, test case generator, test cases
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Tuesday, April 19th, 2016
As I discussed at last week, there are many different engineering roles involved in the development of a large, complex semiconductor device. The EDA industry attempts to serve nearly all of these groups, from the architects and product marketing engineers who dream up the new ideas to the technicians who test production parts on the factory floor. Today I’m focusing on the work of two of EDA’s most traditional customer bases: hardware designers and hardware verification engineers.
Perhaps I’d better explain my title. It comes from an old expression “we went to different schools together” that I remember hearing as a youngster. Sometimes this refers to two people who didn’t actually attend the same school but who are nevertheless longtime close friends. But I’ve also heard it used to refer to two people who did in fact go to school together but had very different experiences. This latter context is the one I have mind for design and verification engineers who work on the same project yet inhabit different worlds.
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Tags: Accellera, assertions, Breker, code coverage, coverage, dvcon, EDA, formal analysis, functional coverage, functional verification, graph, graph-based, IP, portable stimulus, PSWG, reuse, scenario model, SemiconductorEngineering, simulation, SoC verification, system coverage, test generator, uvm
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Wednesday, March 30th, 2016
For those of us who have been in the EDA business on one side or the other (or both), the Design Automation Conference (DAC) is one of the highlights of every year. I almost hate to admit it, but this year holds DAC number 29 for me. I’ve been to San Francisco, San Diego, Los Angeles, Anaheim, Las Vegas, Dallas, New Orleans, and Orlando, most of them multiple times. But one of the most fun locations was Austin, where DAC was held for the first time three years ago, and where we will return in just a few short months.
There will be plenty of time later for us to fill you in on what Breker will be doing at DAC this year. Since the program for the 53rd annual conference just went live, I thought I’d share some initial impressions and predict some likely highlights. Of course as an exhibitor I’m already deep in planning for the show, but I encourage all of you to review the program and start making your own plans. You’ll be sure to have lots of fun in Austin, and on the basis of the information available today I’m sure that this will be a great show.
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Tags: Accellera, austin, Breker, cache coherency, cloud, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IoT, NoC, portable stimulus, scenario model, simulation, SoC verification, uvm, VIP
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Thursday, March 24th, 2016
Last week, we used an update on the Accellera Portable Stimulus Working Group (PSWG) presented at the Design and Verification Conference and Exhibition (DVCon) as a jumping-off point to discuss the status of this standardization effort and some key aspects of the three proposals currently under consideration. We were not the only blog to cover portable stimulus topics from DVCon; Brian Bailey of SemiconductorEngineering and Bernard Murphy from SemiWiki also posted their observations.
Earlier this week, EDACafe blogger colleague Peggy Aycinena posted a thought-provoking look at PSWG and the portable stimulus challenge. In regards to the scope of the proposed standard, she noted “a distinct wow factor in all of this, it’s so comprehensive” and said “this whole effort seems massive to me.” Today we’d like to respond to Peggy’s comments and questions, noting both the challenges of a portable stimulus standard and the availability of a working solution today.
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Tags: Accellera, Breker, bring-up lab, C/C++, cache coherency, Cadence, constraints, EDACafe, emulation, ESL, FPGA, functional verification, graph, graph-based, mentor, multi-SoC, Peggy Aycinena, portable stimulus, prototyping, PSWG, scenario model, SemiconductorEngineering, SemiWIki, simulation, SoC validation, SoC verification, system-on-chip, SystemVerilog, test case generator, test cases
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Wednesday, March 16th, 2016
As all of our regular readers are aware, the software-driven SoC verification space pioneered by Breker is becoming more of a mainstream approach every day. One good barometer for the industry shift now underway is the standardization effort in progress within the Accellera Portable Stimulus Working Group (PSWG). The amount of interest in this standard has skyrocketed recently, and portable stimulus was a hot topic at the Design and Verification Conference and Exhibition (DVCon) two weeks ago.
As we promised when we first began discussing the PSWG, we don’t believe in sharing internal details of standardization work in a public blog. However, the group was offered a slot to present an update at an Accellera-sponsored lunch during DVCon. So the PSWG put together a set of slides with information to share publicly and Vice-Chair Tom Fitzpatrick of Mentor did a nice job of presenting them. For those of you who could not attend, we’ll summarize the current status in today’s blog post.
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Tags: Accellera, Breker, bring-up lab, C/C++, cache coherency, Cadence, constraints, dvcon, emulation, ESL, FPGA, functional verification, graph, graph-based, mentor, multi-SoC, node coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, SystemVerilog, test case generator, test cases, use-case coverage, vayavya
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Wednesday, March 9th, 2016
In last week’s post on The Breker Trekker we summarized activities at the Design and Verification Conference and Exhibition (DVCon) in San Jose, including a brief mention of the “Redefining ESL” panel on Wednesday morning. I attended this session and took detailed notes in anticipation of blogging about it, but in the process gave some thought to my own opinions about the electronic system-level (ESL) domain and how they intersect with those of the panel participants.
The panel was organized by Dave Kelf of OneSpin Solutions and PR guru Nanette Collins, and moderated by Brian Bailey of SemiconductorEngineering. Brian is a long-time observer of the ESL market so I expected him to ask some tough questions. He opened by remarking that the term is generally credited to the late EDA analyst Gary Smith. Many of us who knew Gary sometimes teased him a bit on his regular pronouncements that “this will be the year of ESL.”
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Tags: Accellera, application, Breker, bring-up lab, Cadence, dvcon, emulation, ESL, FPGA, functional verification, graph, high-level synthesis, HLS, Imperas, mentor, node coverage, OneSpin, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, Synopsys, system-on-chip, test case generator, test cases, Universal Verification Methodology, use-case coverage, uvm, virtual platform, virtual prototype
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Thursday, March 3rd, 2016
We’ve just returned from our most important trade show of the year: the Design and Verification Conference and Exhibition (DVCon) in San Jose. Sure, DAC is a bigger show, but it covers all of EDA and so lacks the front-end digital focus of DVCon. We previewed the event over our last few blog posts and today we’d like to summarize what happened and make a prediction or two about how this particular DVCon will affect the industry.
The biggest news for us was that portable stimulus seemed to be on everyone’s lips this year. Many of the engineers who stopped by to visit our booth had heard the term and were aware that the Accellera Portable Stimulus Working Group (PSWG) is developing a standard. If they didn’t know what portable stimulus was, they almost surely knew by the end of the show.
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Tags: Accellera, application, Breker, bring-up lab, cache coherency, Cadence, Cavium, dvcon, emulation, ESL, FPGA, functional verification, graph, graph-based, mentor, multi-SoC, node coverage, path coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekApp, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm
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